Information

PIC18FXX2
DS80122K-page 2 © 2005 Microchip Technology Inc.
3. Module: Data EEPROM
When reading the data EEPROM, the contents of
the EEDATA register may become corrupted in the
second instruction cycle after the RD bit
(EECON1<0>) is set. The actual contents of the
EEPROM remains unaffected.
Work around
To ensure the integrity of the contents of EEDATA,
the register must be read in the instruction imme-
diately following the setting of the RD bit. Use the
MOVF or MOVFF instructions to do this (see
Example 1).
Additionally, all interrupts must be disabled prior to
the read instruction sequence. Interruptions of the
sequence may have the same result of altering the
contents of EEDATA.
EXAMPLE 1: SUGGESTED SEQUENCE
FOR READING EEDATA
Date Codes that pertain to this issue:
All engineering and production devices.
4. Module: Interrupts
Under certain conditions, the use of dual priority
interrupts may cause a program instruction to be
skipped entirely. This has only been observed
when both of the following apply:
• Both high and low interrupts are enabled, and
• A high priority asynchronous interrupt occurs in
the following cycle after any low priority
interrupts.
The event causes the stack to get pushed twice,
and will eventually result in an overflow.
Work around
Two possible solutions are presented. Other
solutions may exist.
1. Enable only high priority interrupts for all
sources, both synchronous and asynchronous.
2. If it is necessary to use both high and low
interrupt priorities:
• Assign asynchronous interrupts as low
priority only.
• Assign synchronous interrupts to both high
and low priority, as needed.
Date Codes that pertain to this issue:
All engineering and production devices.
•
•
BCF INTCON,GIEH ;disable interrupts
;if using interrupts
BSF EECON1,RD ;start the read operation
MOVF EEDATA,W ;move the data out of
;EEDATA
BSF INTCON,GIEH ;enable interrupts
;if using interrupts
•
•
Note: This does not apply to the INT0 (external)
interrupt as it is always configured as a
high priority interrupt.