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PIC18FXX2

The PIC18FXX2 Rev. C0 parts you have received

conform functionally to the Device Data Sheet

(DS39564B), except for the anomalies described

below.

All the issues listed here will be addressed in future

revisions of the PIC18FXX2 silicon.

The following silicon errata apply only to

PIC18FXX2 devices with these Device/Revision

IDs:

1. Module: Core (Program Memory Space)

Performing table read operations above the user

program memory space (addresses over

1FFFFFh) may yield erroneous results at the

extreme low end of the device’s rated temperature

range (-40°C).

This applies specifically to addresses above

1FFFFFh, including the user ID locations

(200000h-200007h), the configuration bytes

(300000h-30000Dh) and the device ID locations

(3FFFFEh and 3FFFFFh). User program memory

is unaffected.

Work around

Three possible work arounds are presented. Other

solutions may exist.

1. Do not perform table read operations on areas

above the user memory space at -40°C.

2. Insert NOP instructions (specifically, literal

FFFFh) around any table read instructions.

The suggested optimal number is 4 instruc-

tions before and 8 instructions after each table

read. This may vary depending upon the

particular application and should be optimized

by the user.

Date Codes that pertain to this issue:

All engineering and production devices.

2. Module: Data EEPROM

When reading the data EEPROM, the contents of

the EEDATA register may be corrupted if the RD

bit (EECON1<0>) is set immediately following a

write to the address byte (EEADR). The actual

contents of the data EEPROM remain unaffected.

Work around

Do not set EEADR immediately before the

execution of a read. Write to EEADR at least one

instruction cycle before setting the RD bit. The

instruction between the write to EEADR and the

read can be any valid instruction, including a NOP.

Date Codes that pertain to this issue:

All engineering and production devices.

Part Number Device ID Revision ID

PIC18F242 00 0100 100 00111

PIC18F252 00 0100 000 00111

PIC18F442 00 0100 101 00111

PIC18F452 00 0100 001 00111

The Device IDs (DEVID1 and DEVID2) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in hexadecimal

in the format “DEVID2 DEVID1”.

PIC18FXX2 Rev. C0 Silicon/Data Sheet Errata

Summary of content (16 pages)

PAGE 1
PIC18FXX2 PIC18FXX2 Rev. C0 Silicon/Data Sheet Errata The PIC18FXX2 Rev. C0 parts you have received conform functionally to the Device Data Sheet (DS39564B), except for the anomalies described below. All the issues listed here will be addressed in future revisions of the PIC18FXX2 silicon. The following silicon errata apply only to PIC18FXX2 devices with these Device/Revision IDs: 2.
PAGE 2
PIC18FXX2 3. Module: MSSP (All I2C™ and SPI™ Modes) The Buffer Full (BF) flag bit of the SSPSTAT register (SSPSTAT<0>) may be inadvertently cleared even when the SSPBUF register has not been read. This will occur only when the following two conditions occur simultaneously: • The four Least Significant bits of the BSR register are equal to 0Fh (BSR<3:0> = 1111) and • Any instruction that contains C9h in its 8 Least Significant bits (i.e., register file addresses, literal data, address offsets, etc.
PAGE 3
PIC18FXX2 6. Module: Program Memory A very small number of applications are experiencing a low failure rate when using selfwrite through code types of applications. The most common of these are bootloader operations. This failure mechanism is characterized by a few bytes in program memory not being written as expected. If this failure is going to occur, it will occur during a self-write operation. If a failure is not immediately observed, then there will be no data retention issues.
PAGE 4
PIC18FXX2 Clarifications/Corrections to the Data Sheet: In the Device Data Sheet (DS39564B), the following clarifications and corrections should be noted. 1. Module: DC Characteristics The values for parameters, D005, D010A, D022A and D022B, shown in Section 22.1 “DC Characteristics” of the Device Data Sheet have changed (modified text is shown in bold): 22.
PAGE 5
PIC18FXX2 22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) (Continued) PIC18LFXX2 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FXX2 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PAGE 6
PIC18FXX2 2. Module: Low-Voltage Detect Characteristics Some of the values for parameter D420 in Table 22-1 of the Device Data Sheet have been updated (modified text is shown in bold). TABLE 22-1: LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol No.
PAGE 7
PIC18FXX2 3. Module: Packaging (Pinout and Product Identification) PIC18F442 and PICF452 devices are now offered in 44-pin, near chip scale micro lead frame packages (commonly known as “QFN”). This packaging type has been added to the product line since the latest revision of the Device Data Sheet. The addition of this option requires the following additions to the Device Data Sheet (DS39564B). The referenced figures and tables follow this text. 1.
PAGE 8
PIC18FXX2 TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS Pin Number Pin Name Pin Buffer DIP PLCC QFN TQFP Type Type 1 MCLR/VPP 2 18 18 MCLR VPP NC — OSC1/CLKI OSC1 13 32 14 33 I ST I ST Master Clear (input) or high-voltage ICSP™ programming enable pin. Master Clear (Reset) input. This pin is an active low Reset to the device. High-voltage ICSP programming enable pin. — — These pins should be left unconnected.
PAGE 9
PIC18FXX2 TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer Type Type DIP PLCC QFN TQFP Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PAGE 10
PIC18FXX2 TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer Type Type DIP PLCC QFN TQFP Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI 15 RC1/T1OSI/CCP2 RC1 T1OSI CCP2 16 RC2/CCP1 RC2 CCP1 17 RC3/SCK/SCL RC3 SCK 18 16 18 19 20 34 35 36 37 32 23 RC5/SDO RC5 SDO 24 RC6/TX/CK RC6 TX CK 25 RC7/RX/DT RC7 RX DT 26 Legend: 25 26 27 29 42 43 44 1 ST — ST Digital I/O. Timer1 oscillator output.
PAGE 11
PIC18FXX2 TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer Type Type DIP PLCC QFN TQFP Description PORTD is a bidirectional I/O port, or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when the PSP module is enabled. RD0/PSP0 19 21 38 38 I/O ST TTL Digital I/O. Parallel Slave Port Data. RD1/PSP1 20 22 39 39 I/O ST TTL Digital I/O. Parallel Slave Port Data.
PAGE 12
PIC18FXX2 FIGURE 3: 44-PIN QFN PACKAGE 44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN) EXPOSED METAL PAD E p D D2 2 1 B n PIN 1 INDEX ON EXPOSED PAD (PROFILE MAY VARY) OPTIONAL PIN 1 INDEX ON TOP MARKING E2 L TOP VIEW BOTTOM VIEW DETAIL: CONTACT VARIANTS A A1 A3 Units Dimension Limits n Number of Contacts p Pitch Overall Height Standoff Base Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Contact Width Contact Length A A1 A3 E E2 D D2 B L MIN
PAGE 13
PIC18FXX2 REVISION HISTORY Rev A Document (10/2003) First revision of this document. Listed silicon issues 1 (Core – Program Memory Space), 2 (Data EEPROM), 3 and 4 (MSSP) and 5 (Core – Instruction Set) and data sheet clarification issues 1 (DC Characteristics), 2 (Low-Voltage Detect Characteristics) and 3 (Packaging – Pinout and Product Identification). Rev B Document (05/2005) Added silicon issue 6 (Reset).
PAGE 15
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 16
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