Information

PIC18FXX2
DS80150D-page 2 © 2005 Microchip Technology Inc.
3. Module: Interrupts
Under certain conditions, the use of dual priority
interrupts may cause a program instruction to be
skipped entirely. This has only been observed
when both of the following apply:
• Both high and low interrupts are enabled, and
• A high priority asynchronous interrupt occurs in
the following cycle after any low priority
interrupt.
The event causes the stack to get pushed twice,
and will eventually result in an overflow.
Work around
Two possible solutions are presented. Other
solutions may exist.
1. Enable only high priority interrupts for all
sources, both synchronous and asynchronous.
2. If it is necessary to use both high and low
interrupt priorities:
• Assign asynchronous interrupts as low
priority only.
• Assign synchronous interrupts to both high
and low priority, as needed.
Date Codes that pertain to this issue:
All engineering and production devices.
4. Module: Core (Program Memory Space)
Performing table read operations above the user
program memory space (addresses over
1FFFFFh) may yield erroneous results at the
extreme low end of the device’s rated temperature
range (-40°C).
This applies specifically to addresses above
1FFFFFh, including the user ID locations
(200000h-200007h), the configuration bytes
(300000h-30000Dh), and the device ID locations
(3FFFFEh and 3FFFFFh). User program memory
is unaffected.
Work around
Three possible work arounds are presented. Other
solutions may exist.
1. Do not perform table read operations on areas
above the user memory space at -40°C.
2. Insert NOP instructions (specifically, literal
FFFFh) around any table read instructions.
The suggested optimal number is 4 instruc-
tions before and 8 instructions after each table
read. This may vary depending upon the
particular application, and should be optimized
by the user.
Date Codes that pertain to this issue:
All engineering and production devices.
5. Module: Data EEPROM
When reading the data EEPROM, the contents of
the EEDATA register may be corrupted if the RD
bit (EECON1<0>) is set immediately following a
write to the address byte (EEADR). The actual
contents of the data EEPROM remain unaffected.
Work around
Do not set EEADR immediately before the
execution of a read. Write to EEADR at least one
instruction cycle before setting the RD bit. The
instruction between the write to EEADR and the
read can be any valid instruction, including a NOP.
Date Codes that pertain to this issue:
All engineering and production devices.
Note: This does not apply to the INT0 (external)
interrupt, as it is always configured as a
high priority interrupt.