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ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SPDIP 28 8-Bit 40 MHz I/O number 23

PIC18FXX2

The PIC18FXX2 Rev. B5 parts you have received con-

form functionally to the Device Data Sheet

(DS39564B), except for the anomalies described

below.

All the issues listed here will be addressed in future

revisions of the PIC18FXX2 silicon.

The following silicon errata apply only to

PIC18FXX2 devices with these Device/Revision

IDs:

1. Module: Program Memory

Data corruption may occur during a table write

operation if a peripheral interrupt also occurs. This

happens only when the interrupt enable bit (PIE or

INTCON register) for the corresponding interrupt

has also been set.

Work around

Before executing any table write instructions, dis-

able ALL peripheral interrupts. This is best done by

clearing all interrupt enable bits in the three Inter-

rupt Control registers (INTCON, INTCON2 and

INTCON3) and both Peripheral Interrupt Enable

registers (PIE1 and PIE2). After the table write is

complete, restore all INTCON and PIE registers to

their pre-instruction state.

Date Codes that pertain to this issue:

All engineering and production devices.

2. Module: Data EEPROM

When reading the data EEPROM, the contents of

the EEDATA register may become corrupted in the

second instruction cycle after the RD bit

(EECON1<0>) is set. The actual contents of the

EEPROM remains unaffected.

Work around

To ensure the integrity of the contents of EEDATA,

the register must be read in the instruction imme-

diately following the setting of the RD bit. Use the

MOVF or MOVFF instructions to do this (see

Example 1).

Additionally, all interrupts must be disabled prior to

the read instruction sequence. Interruptions of the

sequence may have the same result of altering the

contents of EEDATA.

EXAMPLE 1: SUGGESTED SEQUENCE

FOR READING EEDATA

Date Codes that pertain to this issue:

All engineering and production devices.

Part Number Device ID Revision ID

PIC18F242 00 0100 100 00110

PIC18F252 00 0100 000 00110

PIC18F442 00 0100 101 00110

PIC18F452 00 0100 001 00110

The Device IDs (DEVID1 and DEVID2) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in hexadecimal

in the format “DEVID2 DEVID1”.

•

BCF INTCON,GIEH ;disable interrupts

;if using interrupts

BSF EECON1,RD ;start the read operation

MOVF EEDATA,W ;move the data out of

;EEDATA

BSF INTCON,GIEH ;enable interrupts

;if using interrupts

•

PIC18FXX2 Rev. B5 Silicon/Data Sheet Errata

Summary of content (14 pages)

PAGE 1
PIC18FXX2 PIC18FXX2 Rev. B5 Silicon/Data Sheet Errata The PIC18FXX2 Rev. B5 parts you have received conform functionally to the Device Data Sheet (DS39564B), except for the anomalies described below. 2. Module: Data EEPROM When reading the data EEPROM, the contents of the EEDATA register may become corrupted in the second instruction cycle after the RD bit (EECON1<0>) is set. The actual contents of the EEPROM remains unaffected.
PAGE 2
PIC18FXX2 3. Module: Interrupts Under certain conditions, the use of dual priority interrupts may cause a program instruction to be skipped entirely. This has only been observed when both of the following apply: • Both high and low interrupts are enabled, and • A high priority asynchronous interrupt occurs in the following cycle after any low priority interrupt. The event causes the stack to get pushed twice, and will eventually result in an overflow. Work around Two possible solutions are presented.
PAGE 3
PIC18FXX2 6. Module: MSSP (All I2C™ and SPI™ Modes) The Buffer Full (BF) flag bit of the SSPSTAT register (SSPSTAT<0>) may be inadvertently cleared even when the SSPBUF register has not been read. This will occur only when the following two conditions occur simultaneously: • The four Least Significant bits of the BSR register are equal to 0Fh (BSR<3:0> = 1111) and • Any instruction that contains C9h in its 8 Least Significant bits (i.e., register file addresses, literal data, address offsets, etc.
PAGE 4
PIC18FXX2 9. Module: Timer1 Oscillator 10. Module: Reset After the system clock source for the microcontroller is switched from the primary oscillator to the Timer1 oscillator, an increase in system current consumption may occur. It has been observed that in certain Reset conditions, including power-up, the first GOTO instruction at address 0x0000 may not be executed. This occurrence is rare and affects very few applications.
PAGE 5
PIC18FXX2 Clarifications/Corrections to the Data Sheet: In the Device Data Sheet (DS39564B), the following clarifications and corrections should be noted. 1. Module: DC Characteristics Some of the maximum values for parameters D022A and D022B shown in Section 22.1 “DC Characteristics” of the Device Data Sheet have changed (modified text in bold): 22.
PAGE 6
PIC18FXX2 2. Module: Packaging (Pinout and Product Identification) 3. PIC18F442 and PICF452 devices are now offered in 44-pin, near chip-scale micro lead frame packages (commonly known as “QFN”). This packaging type has been added to the product line since the latest revision of the Device Data Sheet. The addition of this option requires the following additions to the Device Data Sheet (DS39564B). The referenced figures and tables follow this text. 2. 5.
PAGE 7
PIC18FXX2 TABLE 1-3: PIC18F442/452 PINOUT I/O DESCRIPTIONS Pin Number Pin Name Pin Buffer Type Type DIP PLCC QFN TQFP MCLR I ST VPP I ST Master Clear (input) or High-Voltage ICSP™ programming enable pin. Master Clear (Reset) input. This pin is an active low Reset to the device. High-Voltage ICSP programming enable pin. — — These pins should be left unconnected.
PAGE 8
PIC18FXX2 TABLE 1-3: PIC18F442/452 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer Type Type DIP PLCC QFN TQFP Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PAGE 9
PIC18FXX2 TABLE 1-3: PIC18F442/452 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer Type Type DIP PLCC QFN TQFP Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI 15 RC1/T1OSI/CCP2 RC1 T1OSI CCP2 16 RC2/CCP1 RC2 CCP1 17 RC3/SCK/SCL RC3 SCK 18 16 18 19 20 34 35 36 37 32 23 RC5/SDO RC5 SDO 24 RC6/TX/CK RC6 TX CK 25 RC7/RX/DT RC7 RX DT 26 25 26 27 29 42 43 44 1 ST — ST Digital I/O. Timer1 oscillator output.
PAGE 10
PIC18FXX2 TABLE 1-3: PIC18F442/452 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer Type Type DIP PLCC QFN TQFP Description PORTD is a bidirectional I/O port, or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled. RD0/PSP0 19 21 38 38 I/O ST TTL Digital I/O. Parallel Slave Port Data. RD1/PSP1 20 22 39 39 I/O ST TTL Digital I/O. Parallel Slave Port Data.
PAGE 11
PIC18FXX2 FIGURE 3: 44-PIN QFN PACKAGE 44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN) EXPOSED METAL PAD E p D D2 2 1 B n PIN 1 INDEX ON EXPOSED PAD (PROFILE MAY VARY) OPTIONAL PIN 1 INDEX ON TOP MARKING E2 L TOP VIEW BOTTOM VIEW DETAIL: CONTACT VARIANTS A A1 A3 Units Dimension Limits n Number of Contacts p Pitch Overall Height Standoff Base Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Contact Width Contact Length A A1 A3 E E2 D D2 B L MIN
PAGE 12
PIC18FXX2 REVISION HISTORY Rev A Document (1/2003) First revision of this document, silicon issues 1 (Program Memory), 2 (Data EEPROM), 3 (Interrupts), and 4 (Core - Program Memory Space), and data sheet clarification 1 (DC Characteristics). Rev B Document (3/2003) Added silicon issues 6, 7 and 8 (MSSP and Core Instruction Set) and data sheet clarification 2 (Packaging - Pinout and Product Identification). Rev C Document (7/2003) Added silicon issue 9 (Timer1 Oscillator).
PAGE 13
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 14
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