Information

© 2007 Microchip Technology Inc. DS80277C-page 13
PIC18F2410/2510/4410/4510
41. Module: MSSP
When the MSSP is configured for SPI mode, the
Buffer Full bit, BF (SSPSTAT<0>), should not be
polled in software to determine when the transfer
is complete.
Work around
Copy the SSPSTAT register into a variable and
perform the bit test on the variable. In Example 6,
SSPSTAT is copied into the working register
where the bit test is performed.
EXAMPLE 6:
A second option is to poll the Master Synchronous
Serial Port Interrupt Flag bit, SSPIF (PIR1<3>).
This bit can be polled and will set when the transfer
is complete.
Date Codes that pertain to this issue:
All engineering and production devices.
42. Module: Reset
This version of silicon does not support the func-
tionality described in Note 1 of parameter D002 in
Section 25.1 “DC Characteristics: Supply
Voltage” of the data sheet. The RAM content may
be altered during a Reset event if the following
conditions are met.
• Device is accessing RAM.
• Asynchronous Reset (i.e., WDT, BOR or MCLR
occurs when a write operation is being
executed (start of a Q4 cycle).
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
43. Module: 10-Bit Analog-to-Digital (A/D)
Converter
When the A/D clock source is selected as 2 TOSC
or RC (when ADCS2:ADCS0 = 000 or x11), in
extremely rare cases, the E
IL (Integral Linearity
Error) and E
DL (Differential Linearity Error) may
exceed the data sheet specification at codes 511
and 512 only.
Work around
Select a different A/D clock source (4 TOSC,
8T
OSC, 16 TOSC, 32 TOSC, 64 TOSC) and avoid
selecting the 2 T
OSC or RC modes.
Date Codes that pertain to this issue:
All engineering and production devices.
loop_MSB:
MOVF SSPSTAT, W
BTFSS WREG, BF
BRA loop_MSB