Information

PIC18F2410/2510/4410/4510
DS80277C-page 12 © 2007 Microchip Technology Inc.
37. Module: Timer1
In 16-Bit Asynchronous Counter mode (with or
without use of the Timer1 oscillator), the TMR1H
and TMR3H buffers do not update when TMRxL is
read.
This issue only affects reading the TMRxH regis-
ters. The timers increments and set the interrupt
flags as expected. The timer registers can also be
written as expected.
Work around
1. Use 8-bit mode by clearing the RD16 bit
(T1CON<7>).
2. Use the internal clock synchronization option
by clearing the T1SYNC
bit (T1CON<2>).
Date Codes that pertain to this issue:
All engineering and production devices.
38. Module: MSSP
The MSSP configured in SPI slave mode will gener-
ate a write collision if SSPBUF is updated and the
previous SSPBUF contents have not been
transferred
to the shift register.
Reinitializing the MSSP by clearing and setting the
SSPEN (SSPCON1<5>) bit prior to rewriting
SSPBUF will not prevent the error condition.
Work around
Prior to updating the SSPBUF register with a new
value, verify whether the previous contents were
transferred by reading the BF (SSPSTAT<0>) bit. If
the previous byte has not been transferred, update
SSPBUF and clear the WCOL (SSPCON1<7>) bit if
necessary.
Date Codes that pertain to this issue:
All engineering and production devices.
39. Module: MSSP
In SPI mode, the SDO output may change after the
inactive clock edge of the bit 0 output. This may
affect some SPI components that read data over
300 ns after the inactive edge of SCK.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
40. Module: MSSP
It has been observed that, following a Power-on
Reset, I
2
C mode may not initialize properly by just
configuring the SCL and SDA pins as either inputs
or outputs. This has only been seen in a few
unique system environments.
A test of a statistically significant sample of pre-
production systems, across the voltage and
current range of the application's power supply,
should indicate if a system is susceptible to this
issue.
Work around
Before configuring the module for I
2
C operation:
1. Configure the SCL and SDA pins as outputs by
clearing their corresponding TRIS bits.
2. Force SCL and SDA low by clearing the
corresponding LAT bits.
3. While keeping the LAT bits clear, configure
SCL and SDA as inputs by setting their TRIS
bits.
Once this is done, use the SSPCON1 and
SSPCON2 registers to configure the proper I
2
C
mode as before.
Date Codes that pertain to this issue:
All engineering and production devices.