Datasheet

PIC18(L)F2X/4XK22
DS41412F-page 338  2010-2012 Microchip Technology Inc.
FIGURE 20-1: DIVSRCLK BLOCK DIAGRAM
FIGURE 20-2: SR LATCH SIMPLIFIED BLOCK DIAGRAM
3
SRCLK<2:0>
Peripheral
Clock
DIVSRCLK
Programmable
SRCLK divider
1:4 to 1:512
Tosc
4
-
5
1
2
c
y
c
l
e
s
.
.
.
SRCLK<2:0> = "001"
1:8
t0+4t0 t0+8 t0+12
SRPS
S
R
Q
Q
Note 1: If R = 1 and S = 1 simultaneously, Q = 0, Q = 1
2: Pulse generator causes a pulse width of 2 T
OSC clock cycles.
3: Name denotes the connection point at the comparator output.
Pulse
Gen
(2)
SR
Latch
(1)
SRQEN
SRSPE
SRSC2E
SRSCKE
DIVSRCLK
sync_C2OUT
(3)
SRSC1E
sync_C1OUT
(3)
SRPR
Pulse
Gen
(2)
SRRPE
SRRC2E
SRRCKE
DIVSRCLK
sync_C2OUT
(3)
SRRC1E
sync_C1OUT
(3)
SRLEN
SRNQEN
SRLEN
SRQ
SRNQ
SRI
SRI