Datasheet

PIC18(L)F2X/4XK22
DS41412F-page 312  2010-2012 Microchip Technology Inc.
FIGURE 18-2: COMPARATOR C1/C2 SIMPLIFIED BLOCK DIAGRAM
Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (F
OSC).
3: Q1 is held high during Sleep mode.
4: Synchronized comparator output should not be used to gate Timer1 in conjunction with synchronized T1CKI.
Cx
CxPOL
to PWM Logic
0
1
2
3
CxON
(1)
CxCH<1:0>
2
0
1
CxR
CM2CON1 (MCxOUT)
To Interrupts
CxV IN -
CxV IN +
C12IN0-
C12IN1-
C12IN2-
C12IN3-
CxIN+
DQ
EN
Q1
(2),(3)
DQ
EN
CL
Read or Write
Reset
+
-
0
1
DAC Output
C
XRSEL
FVR BUF1
CxSP
C
XVREF
CxOE
C xOUT
Timer1 Clock
DQ
sync_C xOUT
To CMxCON0 (CxOUT)
(CxIF)
of CMxCON0
Q3
(2)
0
1
CxSYNC
async_CXOUT
TRIS bit
- to SR Latch
- to TxG MUX
(4)