Datasheet

 2010-2012 Microchip Technology Inc. DS41412F-page 249
PIC18(L)F2X/4XK22
FIGURE 15-29: I
2
C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
P
9
87
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4
A3 A2 A1
SDAx SCLx
12
3
4
5
6
7
8
9
12
3
4
5
678 9
1234
Bus master terminates
transfer
ACK
Receiving Data from Slave
Receiving Data from Slave
D0
D1
D2
D3D4
D5
D6D7
ACK
Transmit Address to Slave
SSPxIF BF
ACK is not sent
Write to SSPxCON2<0>(SEN = 1),
Write to SSPxBUF occurs here,
ACK from Slave
Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1)
PEN bit = 1 written here
Data shifted in on falling edge of CLK
Cleared by software
start XMIT
SEN = 0
SSPxOV
SDAx = 0, SCLx = 1
while CPU
(SSPxSTAT<0>)
ACK
Cleared by software
Cleared by software
Set SSPxIF interrupt at end of receive
Set P bit (SSPxSTAT<4>) and SSPxIF
Cleared in software
ACK from Master
Set SSPxIF at end
Set SSPxIF interrupt at end of Acknowledge sequence
Set SSPxIF interrupt at end of Acknow- ledge sequence
of receive
Set ACKEN, start Acknowledge sequence
SSPxOV is set because SSPxBUF is still full
SDAx = ACKDT = 1
RCEN cleared automatically
RCEN = 1, start next receive
Write to SSPxCON2<4> to start Acknowledge sequence SDAx = ACKDT (SSPxCON2<5>) = 0
RCEN cleared automatically
responds to SSPxIF
ACKEN
begin Start condition
Cleared by software
SDAx = ACKDT = 0
Last bit is shifted into SSPxSR and contents are unloaded into SSPxBUF
RCEN
Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1)
RCEN cleared automatically
ACK from Master
SDAx = ACKDT = 0
RCEN cleared automatically
R/W