Datasheet

PIC18(L)F2X/4XK22
DS41412F-page 152  2010-2012 Microchip Technology Inc.
TABLE 10-14: PORTE I/O SUMMARY
Pin Function
TRIS
Setting
ANSEL
Setting
Pin
Type
Buffer
Type
Description
RE0/P3A/CCP3/AN5 RE0 00O DIG LATE<0> data output; not affected by analog input.
10I ST PORTE<0> data input; disabled when analog input
enabled.
P3A
(1)
00O DIG Enhanced CCP3 PWM output.
CCP3
(1)
00
ODIG
Compare 3 output/PWM 3 output.
10
IST
Capture 3 input.
AN5 11I AN Analog input 5.
RE1/P3B/AN6 RE1 00O DIG LATE<1> data output; not affected by analog input.
10I ST PORTE<1> data input; disabled when analog input
enabled.
P3B
00O DIG Enhanced CCP3 PWM output.
AN6 11I AN Analog input 6.
RE2/CCP5/AN7 RE2 00O DIG LATE<2> data output; not affected by analog input.
10I ST PORTE<2> data input; disabled when analog input
enabled.
CCP5
00O DIG Compare 5 output/PWM 5 output.
10I ST Capture 5 input.
AN7 11I AN Analog input 7.
RE3/V
PP/MCLR
RE3 — — I ST PORTE<3> data input; enabled when Configuration bit
MCLRE = 0.
V
PP — — P AN Programming voltage input; always available
MCLR
——
I ST Active-low Master Clear (device Reset) input; enabled
when configuration bit MCLRE = 1.
Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS
= CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I
2
C
TM
= Schmitt Trigger input with I
2
C.
Note 1: Alternate pin assignment for P3A/CCP3 when Configuration bit CCP3MX is clear.
TABLE 10-15: REGISTERS ASSOCIATED WITH PORTE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
ANSELE
(1)
— — — — — ANSE2 ANSE1 ANSE0 156
INTCON2 RBPU
INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 117
LATE
(1)
— — — — — LATE2 LATE1 LATE0 157
PORTE
— — — —RE3
RE2
(1)
RE1
(1)
RE0
(1)
154
SLRCON — — —SLRE
(1)
SLRD
(1)
SLRC SLRB SLRA 158
TRISE WPUE3
— — — — TRISE2
(1)
TRISE1
(1)
TRISE0
(1)
156
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTE.
Note 1: Available on PIC18(L)F4XK22 devices.