Datasheet
PIC18(L)F2X/4XK22
DS41412F-page 126 2010-2012 Microchip Technology Inc.
REGISTER 9-11: PIE3: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 3
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SSP2IE: TMR5 Gate Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 6 BCL2IE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5 RC2IE: EUSART2 Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4 TX2IE: EUSART2 Transmit Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 3 CTMUIE: CTMU Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 2 TMR5GIE: TMR5 Gate Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 1 TMR3GIE: TMR3 Gate Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 0 TMR1GIE: TMR1 Gate Interrupt Enable bit
1 = Enabled
0 =Disabled