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 2009-2011 Microchip Technology Inc. DS80469D-page 1

PIC18F23/43K20

The PIC18F23/43K20 family devices that you have

received conform functionally to the current Device Data

Sheet (DS41303G), except for the anomalies described

in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the PIC18F23/43K20 silicon.

Data Sheet clarifications and corrections start on page 6,

following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 2,

MPLAB ICD 3, PICkit™ 2 or PICkit 3:

1. Using the appropriate interface, connect the

device to the MPLAB ICD 2 programmer/

debugger, PICkit 2 or PICkit 3.

2. From the main menu in MPLAB IDE, select

onfigure>Select Device, and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Programmer

>Select Tool).

4. Perform a “Connect” operation to the device

(Programmer

>Connect). Depending on the

development tool used, the part number and

Device Revision ID value appear in the Output

window.

The Device ID values for the various devices and

silicon revisions are shown in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (B0).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

Revision ID for Silicon Revision

(2)

A0 A1 B0

PIC18F23K20 20E0h 00h 01h 02h

PIC18F43K20 20C0h 00h 01h 02h

Note 1: The device and revision data is stored in the Device ID located at 3FFFFE:3FFFFFh in Configuration and

ID memory.

2: Refer to the “PIC18F2XK20/4XK20 Memory Programming Specification” (DS41297) for detailed

information.

PIC18F23/43K20 Family

Silicon Errata and Data Sheet Clarification

Summary of content (10 pages)

PAGE 1
PIC18F23/43K20 PIC18F23/43K20 Family Silicon Errata and Data Sheet Clarification The PIC18F23/43K20 family devices that you have received conform functionally to the current Device Data Sheet (DS41303G), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2.
PAGE 2
PIC18F23/43K20 TABLE 2: SILICON ISSUE SUMMARY (PIC18F23/43K20) Module BOR Feature Item Number Issue Summary Affected Revisions(1) A0 A1 X X B0 Reset 1. Unexpected Reset when using comparator. Comparator Comparator 2. Output glitch with FVR selected for ADC. ECCP Full-Bridge 3. Dead band time is 4/FOSC instead of 1/FOSC. X X X ECCP Full-Bridge 4. Compromised dead band. X X X MSSP (SPI clock) SPI clock 5. Improper start in Timer2/2 Clock mode.
PAGE 3
PIC18F23/43K20 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (B0). 1. Module: BOR An unexpected Brown-out Reset may occur when enabling the comparator with the Fixed Voltage Reference (FVR) selected as the VIN+ input.
PAGE 4
PIC18F23/43K20 6. Module: MSSP (SPI Master mode) 8. Module: MSSP (Master I2C™ mode) none. In Master I2C Receive mode, if a Stop condition occurs in the middle of an address or data reception, then the SCL clock stream will continue endlessly and the RCEN bit of the SSPCON2 register will remain set improperly. When a Start condition occurs after the improper Stop condition, then 9 additional clocks will be generated followed by the RCEN bit going low.
PAGE 5
PIC18F23/43K20 10. Module: EUSART In Asynchronous Receive mode, the RCIDL bit of the BAUDCON register will properly go low when an invalid Start bit less than 1/16th of a bit time is received. The RCIDL bit will then properly go high 1/8th of a bit time later. However, if another invalid Start bit occurs less than 1 bit time after the leading edge of the first invalid Start bit then the RCIDL bit will improperly stay high then improperly go low one bit time later.
PAGE 6
PIC18F23/43K20 Data Sheet Clarifications The following typographical corrections and clarifications are to be noted for the latest version of the device data sheet (DS41303G): None. DS80469D-page 6  2009-2011 Microchip Technology Inc.
PAGE 7
PIC18F23/43K20 APPENDIX A: DOCUMENT REVISION HISTORY Rev. A Document (4/2009) First revision of this document. Data Sheet Clarification: Added Module 1: MSSP I2C™ (Table 17-3); Module 2: ADC (Equation 19-1); Module 3: Interrupts. Added Module 1: ECCP; Module 2: ECCP; Module 3: MSSP; Module 4: MSSP; Module 5: MSSP; Module 6: MSSP; Module 7: EUSART; Module 8: EUSART; Module 9: Data EEPROM Memory; Module 10: Program Flash Memory; Added Module 11: ADC. Rev. B Document (9/2009) Added Silicon Revision A1.
PAGE 8
PIC18F23/43K20 NOTES: DS80469D-page 8  2009-2011 Microchip Technology Inc.
PAGE 9
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 10
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