Datasheet

 2010 Microchip Technology Inc. DS41303G-page 39
PIC18F2XK20/4XK20
FIGURE 2-7: CLOCK SWITCH TIMING
Old Clock
New Clock
IRCF <2:0>
System Clock
Start-up Time
(1)
Clock Sync Running
High Speed Low Speed
Select Old
Select New
New Clk Ready
Low Speed High Speed
Old Clock
New Clock
IRCF <2:0>
System Clock
Start-up Time
(1)
Clock Sync Running
Select Old Select New
New Clk Ready
Note 1: Start-up time includes TOST (1024 TOSC) for external clocks, plus TPLL (approx. 2 ms) for HSPLL mode.