Datasheet

 2010 Microchip Technology Inc. DS41303G-page 245
PIC18F2XK20/4XK20
FIGURE 18-5: ASYNCHRONOUS RECEPTION
TABLE 18-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 59
PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 62
PIE1
PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 62
IPR1 PSPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 62
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 61
RCREG EUSART Receive Register 61
TRISC TRISC7
TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 62
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 61
BAUDCON ABDOVF RCIDL DTRXP
CKTXP BRG16 — WUE ABDEN 61
SPBRGH EUSART Baud Rate Generator Register, High Byte 61
SPBRG EUSART Baud Rate Generator Register, Low Byte 61
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Reserved in PIC18F2XK20 devices; always maintain these bits clear.
Start
bit
bit 7/8
bit 1bit 0
bit 7/8
bit 0Stop
bit
Start
bit
Start
bit
bit 7/8
Stop
bit
RX/DT pin
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
RCIDL