Information

 2009-2011 Microchip Technology Inc. DS80469D-page 5
PIC18F23/43K20
10. Module: EUSART
In Asynchronous Receive mode, the RCIDL bit of
the BAUDCON register will properly go low when
an invalid Start bit less than 1/16th of a bit time is
received. The RCIDL bit will then properly go high
1/8th of a bit time later. However, if another invalid
Start bit occurs less than 1 bit time after the leading
edge of the first invalid Start bit then the RCIDL bit
will improperly stay high then improperly go low
one bit time later. The RCIDL bit will then stay low
improperly until a valid Start bit is received.
Work around
When monitoring the RCIDL bit, measure the
length of time between the RCIDL going low and
the RCIF flag going high. If this time is greater than
one character time then restore the RCIDL bit by
resetting the EUSART module. The EUSART
module is reset when the SPEN bit of the RCSTA
register is cleared.
Affected Silicon Revisions
PIC18F23/43K20
11. Module: Data EEPROM Memory
The write/erase endurance of Data EE Memory is
limited to 10K cycles.
Work around
Use error correction method that stores data in
multiple locations.
Affected Silicon Revisions
PIC18F23/43K20
12. Module: Program Flash Memory
The write/erase endurance of the Program Flash
Memory is limited to 1K cycles when V
DD is above
3V. Endurance degrades when V
DD is below 3V.
Work around
For data tables in Program Flash Memory use
error correction method that stores data in multiple
locations.
Affected Silicon Revisions
PIC18F23/43K20
13. Module: ADC
After extended stress the Most Significant bit
(MSb) of the ADC conversion result can become
stuck at ‘0’. Conversions resulting in code 511 or
less are still accurate, but conversions that
should result in codes greater than 511 are
instead pinned at 511.
The potential for failures is a function of several
factors:
• The potential for failures increases over the
life of the part. No failures have ever been
seen for accelerated stress estimated to be
equivalent to 34 years at room temperature.
The failure rate after accelerated stress esti-
mated to be equivalent to 146 years at room
temperature can be as high as 10% for V
DD =
1.8V. The time to failure will decrease as the
operating temperature increases.
• The potential for failures is highest at low V
DD
and decreases as V
DD increases.
Work around
1. Restrict the input voltage to less than 1/2 of
the ADC voltage reference so that the
expected result is always a code less than
or equal to 511.
2. Use manual acquisition time (ACQT<2:0> =
000) and put the part to Sleep after each
conversion.
Affected Silicon Revisions
PIC18F23/43K20
A0 A1
B0
XX
X
A0 A1
B0
XX
A0 A1 B0
XX
A0 A1 B0
X