Information

PIC18F23/43K20
DS80469D-page 4  2009-2011 Microchip Technology Inc.
6. Module: MSSP (SPI Master mode)
In SPI Master mode, when the CKE bit of the
SSPSTAT register is cleared and the SMP bit of
the SSPSTAT register is set, then the last bit of the
incoming data stream (bit 0) at the SDI pin will not
be sampled properly.
Work around
none.
Affected Silicon Revisions
PIC18F23/43K20
7. Module: MSSP (SPI Master mode)
In SPI Master mode, if the SSPBUF register is writ-
ten while a byte is actively being transmitted, an
extra clock pulse will be improperly generated at
the end of the transmission. Further writes to the
SSPBUF register will be inhibited although 8 or 9
clock pulses will be generated for each attempted
write. The WCON bit of the SSPCON register is
properly set indicating that a write collision
occurred. However, the write collision condition
can only be cleared by resetting the MSSP mod-
ule. Clear the MSSP by clearing the SSPEN bit of
the SSPCON1 register.
Work around
Use the SSPIF bit of the PIR1 register or the BF bit
of the SSPSTAT register to determine that the
transmission is complete before writing the
SSPBUF register. In the event that a write collision
does occur, use the Slave Select feature to
resynchronize the Slave clock.
Affected Silicon Revisions
PIC18F23/43K20
8. Module: MSSP (Master I
2
C™ mode)
In Master I
2
C Receive mode, if a Stop condition
occurs in the middle of an address or data
reception, then the SCL clock stream will continue
endlessly and the RCEN bit of the SSPCON2
register will remain set improperly. When a Start
condition occurs after the improper Stop condition,
then 9 additional clocks will be generated followed
by the RCEN bit going low.
Work around
Use low-impedance pull-ups on the SDA line to
reduce the possibility of noise glitches, which may
trigger an improper Stop event. Use a time-out
event timer to detect the unexpected Stop condi-
tion and resulting stuck RCEN bit. Clear stuck
RCEN bit by clearing SSPEN bit of SSPCON1.
Affected Silicon Revisions
PIC18F23/43K20
9. Module: EUSART
The OERR flag of the RCSTA register is reset only
by clearing the CREN bit of the RCSTA register or
by a device Reset. Clearing the SPEN bit of the
RCSTA register does not clear the OERR flag.
Work around
Clear the OERR flag by clearing the CREN bit
instead of clearing the SPEN bit.
Affected Silicon Revisions
PIC18F23/43K20
A0 A1
B0
XX
X
A0 A1
B0
XX
X
A0 A1 B0
XX
X
A0 A1
B0
XX
X