Information

PIC18F23/43K20
DS80469D-page 2  2009-2011 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY (PIC18F23/43K20)
Module Feature
Item
Number
Issue Summary
Affected
Revisions
(1)
A0 A1 B0
BOR Reset 1. Unexpected Reset when using comparator. X X
Comparator Comparator 2. Output glitch with FVR selected for ADC. X
ECCP Full-Bridge 3. Dead band time is 4/F
OSC instead of 1/FOSC.X X X
ECCP Full-Bridge 4. Compromised dead band. X X X
MSSP (SPI clock) SPI clock 5. Improper start in Timer2/2 Clock mode. X X X
MSSP (SPI Mas-
ter mode)
SPI Master 6. Improper sampling of last bit. X X X
MSSP (SPI Mas-
ter mode)
SPI Master 7. Write collision on transmission. X X X
MSSP (Master
I2C™ mode)
I
2
C™ Master 8. Improper handling of Stop event. X X X
EUSART OERR Flag 9. Clearing SPEN bit does not clear OERR flag. X X X
EUSART BAUDCON 10. RCIDL may improperly stay low. X X X
Data EEPROM
Memory
Endurance 11. Endurance limited to 10K cycles. X X
Program Flash
Memory
Endurance 12. Endurance limited to 1K cycles. X X
ADC ADC Conversion 13. ADC conversion may be limited to half scale. X
Note 1: Only those issues indicated in the last column apply to the current silicon revision.