Information

PIC18F2331/2431/4331/4431
DS80180C-page 2 © 2005 Microchip Technology Inc.
4. Module: PCPWM
When the PCPWM is operated in Center-Aligned
mode with double updates and the duty cycle
alternates on each update between a zero and
non-zero value, an incorrect waveform is gener-
ated (the PWM output will alternate between one
PWM period high and one PWM period low). If in
Complementary mode, dead time will not be
inserted properly.
Work around
Do not use zero duty cycle when in Center-Aligned
mode with double updates. Instead of zero, set the
duty cycle to a small, non-zero value.
Date Codes that pertain to this issue:
All engineering and production devices.
5. Module: PCPWM
When the PCPWM is operated in Center-Aligned
mode with double updates and the duty cycle
alternates on each update between a greater than
100% duty cycle and a non-zero value, an incorrect
waveform is generated.
Work around
Do not use equal to or greater than 100% duty cycle
when in Center-Aligned mode with double updates.
Ensure that the maximum duty cycle value is
always smaller than or equal to the PWM period,
i.e., PDCH:PDCL ≤ (4 * (PTPERH:PTPERL)).
Date Codes that pertain to this issue:
All engineering and production devices.
6. Module: PCPWM
If dead-time insertion is enabled and it is a non-
zero value, glitches in the PWM output will occur
under the following conditions:
1. When the PWM Timer is stopped by clearing
the PTEN bit.
2. When the duty cycle is changed to zero.
Work around
1. Before disabling the PWM timer, ensure that
PORTB is set up to maintain a safe state of
external hardware and that TRISB is set up to
define the pins as outputs.
2. Do not use zero duty cycle when dead-time
insertion is enabled. Instead of zero, set the
duty cycle to a small, non-zero value (such as
‘1’).
Date Codes that pertain to this issue:
All engineering and production devices.
7. Module: PCPWM
The PTMRH register will read as ‘00’ or the last
value written to it, even though the upper four bits
of the PWM timer may be different. Writing to
PTMRH will effect the upper four bits of the PWM
timer when PTMRL is subsequently written.
Although the PWM timer operates correctly, the
double-buffer circuit does not transfer data to the
PTMRH register from the upper four bits of the
PWM timer.
Work around
PWM operation is not affected. Do not attempt to
read PTMRH.
Date Codes that pertain to this issue:
All engineering and production devices.
8. Module: PCPWM
In Complementary mode with dead-time insertion,
when using OVDCOND and OVDCONS to
override the PWM outputs, dead time is not
inserted correctly when the dead-time prescaler is
F
OSC/4, FOSC/8 or FOSC/16.
Work around
None. Use dead-time prescaler of FOSC/2 in these
circumstances.
Date Codes that pertain to this issue:
All engineering and production devices.
9. Module: Data EEPROM
When writing to the data EEPROM, the contents of
the data EEPROM memory may not be written as
expected if the internal voltage reference is not
enabled.
Work around
Either of two work arounds can be used:
1. Before beginning any writes to the data
EEPROM, enable the LVD (any voltage) and
wait for the internal voltage reference to
become stable. LVD interrupt requests may be
ignored. Once the LVD voltage reference is
stable, perform all EEPROM writes normally.
When writes have been completed, the LVD
may be disabled.
2. Configure the BOR as enabled (any voltage).
Select a threshold below V
DD to allow normal
operation. If V
DD is below the BOR threshold,
the device will be held in Brown-out Reset.