Information

PIC18F2331/2431/4331/4431
DS80192C-page 2 © 2005 Microchip Technology Inc.
4. Module: PCPWM
If dead-time insertion is enabled and it is a non-
zero value, glitches in the PWM output will occur
under the following conditions:
1. When the PWM timer is stopped by clearing
the PTEN bit.
2. When the duty cycle is changed to zero.
Work around
1. Before disabling the PWM timer, ensure that
PORTB is set up to maintain a safe state of
external hardware and that TRISB is set up to
define the pins as outputs.
2. Do not use zero duty cycle when dead-time
insertion is enabled. Instead of zero, set the
duty cycle to a small, non-zero value (such as
‘1’).
Date Codes that pertain to this issue:
All engineering and production devices.
5. Module: PCPWM
The PTMRH register will read as ‘00’ or the last
value written to it, even though the upper four bits
of the PWM timer may be different. Writing to
PTMRH will effect the upper four bits of the PWM
timer when PTMRL is subsequently written.
Although the PWM timer operates correctly, the
double-buffer circuit does not transfer data to the
PTMRH register from the upper four bits of the
PWM timer.
Work around
PWM operation is not affected. Do not attempt to
read PTMRH.
Date Codes that pertain to this issue:
All engineering and production devices.
6. Module: PCPWM
In Complementary mode with dead-time insertion,
when using OVDCOND and OVDCONS to
override the PWM outputs, dead time is not
inserted correctly when the dead-time prescaler is
FOSC/4, FOSC/8 or FOSC/16.
Work around
None. Use dead-time prescaler of FOSC/2 in these
circumstances.
Date Codes that pertain to this issue:
All engineering and production devices.
7. Module: Core (DAW Instruction)
The DAW instruction may improperly clear the
Carry bit (STATUS<0>) when executed.
Work around
Test the Carry bit state before executing the DAW
instruction. If the Carry bit is set, increment the
next higher byte to be added, using an instruction
such as INCFSZ (this instruction does not affect
any Status flags and will not overflow a BCD
nibble). After the DAW instruction has been
executed, process the Carry bit normally (see
Example 1).
EXAMPLE 1: PROCESSING THE CARRY
BIT DURING BCD ADDITIONS
Date Codes that pertain to this issue:
All engineering and production devices.
8. Module: EUSART
Bit SENDB in the TXSTA register is not automati-
cally cleared by hardware upon completion of
transmission of a Sync Break.
Work around
Check the TRMT bit in TXSTA. If the TRMT bit is
set, Break transmission is said to be complete.
9. Module: EUSART
If the transmitter is left enabled while the module is
performing an auto-baud operation, an arbitrary
data byte may get transmitted.
Work around
Clear TXEN bit (TXSTA<5>) before any auto-baud
operation and set it after auto-baud is complete.
Enable TXEN only when a data byte is to be
transmitted. Care must be taken to ensure that the
TX pin is pulled high, either through an external
resistor, or by making the TX pin an output and
writing ‘1’ to it, to not disturb the transmit line.
MOVLW 0x80 ; .80 (BCD)
ADDLW 0x80 ; .80 (BCD)
BTFSC STATUS, C ; test C
INCFSZ byte2 ; inc next higher LSB
DAW
BTFSC STATUS, C ; test C
INCFSZ byte2 ; inc next higher LSB
This is repeated for each DAW instruction.