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PIC18F2331/2431/4331/4431

The PIC18F2331/2431/4331/4431 parts you have

received conform functionally to the Device Data Sheet

(DS39616), except for the anomalies described below.

Any Data Sheet Clarification issues related to the

PIC18F2331/2431/4331/4431 will be reported in a

separate Data Sheet errata. Please check the

Microchip web site for any existing issues.

All the issues listed here will be addressed in future

revisions of the PIC18F2331/2431/4331/4431 silicon.

The following silicon errata apply only to

PIC18F2331/2431/4331/4431 devices with these

Device/Revision IDs:

1. Module: PCPWM

When the PCPWM is operated in Complementary

mode with a non-zero dead-time value and the

duty cycle results in an active-low time of less than

CY, the PWM generator will miss the rising edge

for a new PWM period and the PWM output will

alternate between one PWM period high and one

PWM period low.

Work around

When in Complementary mode with a non-zero

dead-time value, ensure that the active-low time

will always be greater than 1 TCY. In other words,

when dead time is not equal to zero, ensure that:

PDCH:PDCL < (4 * PTPERH:PTPERL)

PDCH:PDCL > (4 * (PTPERH:PTPERL + 1))

Date Codes that pertain to this issue:

All engineering and production devices.

2. Module: PCPWM

When the PCPWM is operated in Center-Aligned

mode with double updates and the duty cycle

alternates on each update between a zero and

non-zero value, an incorrect waveform is gener-

ated (the PWM output will alternate between one

PWM period high and one PWM period low). If in

Complementary mode, dead time will not be

inserted properly.

Work around

Do not use zero duty cycle when in Center-Aligned

mode with double updates. Instead of zero, set the

duty cycle to a small, non-zero value.

Date Codes that pertain to this issue:

All engineering and production devices.

3. Module: PCPWM

When the PCPWM is operated in Center-Aligned

mode with double updates and the duty cycle

alternates on each update between a greater than

100% duty cycle and a non-zero value, an incorrect

waveform is generated.

Work around

Do not use equal to or greater than 100% duty cycle

when in Center-Aligned mode with double updates.

Ensure that the maximum duty cycle value is

always smaller than or equal to the PWM period,

i.e., PDCH:PDCL ≤ (4 * (PTPERH:PTPERL)).

Date Codes that pertain to this issue:

All engineering and production devices.

Part Number Device ID Revision ID

PIC18F2331 00 1000 111 00010

PIC18F2431 00 1000 110 00010

PIC18F4331 00 1000 101 00010

PIC18F4431 00 1000 100 00010

The Device IDs (DEVID1 and DEVID2) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in hexadecimal

in the format “DEVID2 DEVID1”.

PIC18F2331/2431/4331/4431 Rev. A3 Silicon Errata

Summary of content (6 pages)

PAGE 1
PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 Rev. A3 Silicon Errata The PIC18F2331/2431/4331/4431 parts you have received conform functionally to the Device Data Sheet (DS39616), except for the anomalies described below. Any Data Sheet Clarification issues related to the PIC18F2331/2431/4331/4431 will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues.
PAGE 2
PIC18F2331/2431/4331/4431 4. Module: PCPWM If dead-time insertion is enabled and it is a nonzero value, glitches in the PWM output will occur under the following conditions: 1. When the PWM timer is stopped by clearing the PTEN bit. 2. When the duty cycle is changed to zero. Work around 1. Before disabling the PWM timer, ensure that PORTB is set up to maintain a safe state of external hardware and that TRISB is set up to define the pins as outputs. 2.
PAGE 3
PIC18F2331/2431/4331/4431 10. Module: EUSART 14. Module: EUSART This module may perform incorrect auto-baud calculation if the ABDEN (BAUDCTL<0>) bit was set while the receive pin was at a low level. The EUSART cannot receive asynchronous data at the four fastest baud rates (BRGH = 1, BRG16 = 1 and SPBRG < 4). Work around Work around Wait for the RX pin to go high and then set the ABDEN bit. Use a slower baud rate or a faster system clock speed. 11.
PAGE 4
PIC18F2331/2431/4331/4431 REVISION HISTORY Rev A Document (6/2004) First revision of this document. Silicon issues 1-6 (PCPWM), 7 (Core – DAW Instruction) and 8-14 (EUSART) and Data Sheet Clarification issues 1 (Poweron Reset), 2 (Watchdog Timer), 3 (PWM Equations), 4 (DC Characteristics) and 5 (LVD Characteristics). Rev B Document (12/2004) Added Data Sheet Clarification issue 6 (28-Pin QFN Diagram). Rev C Document (05/2005) Added silicon issue 15 (HSADC).
PAGE 5
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 6
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