Information
© 2007 Microchip Technology Inc. DS80132F-page 3
SSP MODULE
3. Module: SSP (I
2
C Mode)
The description of the I
2
C pins related to the TRIS
bits is clarified. To ensure proper communication
of the I
2
C Slave mode, the TRIS bits (TRISx [SDA,
SCL]) corresponding to the I
2
C pins must be set to
‘1’. If any TRIS bits (TRISx<7:0>) of the port con-
taining the I
2
C pins (PORTx [SDA, SCL]) are
changed in software during I
2
C communication
using a Read-Modify-Write instruction (BSF, BCF),
then the I
2
C mode may stop functioning properly
and I
2
C communication may suspend. Do not
change any of the TRISx bits (TRIS bits of the port
containing the I
2
C pins) using the instruction BSF
or BCF during I
2
C communication. If it is absolutely
necessary to change the TRISx bits during
communication, the following method can be
used:
Note: This correction applies to the Data Sheets
for the following devices:
• PIC14000 (DS40122B)
• PIC16C6X (DS30234D) except
PIC16C61 (does not implement SSP
module)
• PIC16C62B/72A (DS35008B)
• PIC16C63A/65B/73B/74B (DS30605C)
• PIC16C72/73/73A/74/74A/76/77
(DS30390E)
• PIC16C923/924 (DS30444E)
• PIC16C925/926 (DS39544A)
• PIC16F72 (DS39597B)
• PIC16F73/74/76/77 (DS30325B)
MOVF TRISC, W ; Example for a 40-pin part such as the PIC16F73
IORLW 0x18 ; Ensures <4:3> bits are ‘11’
ANDLW B’11111001’ ; Sets <2:1> as output, but will not alter other bits
; User can use their own logic here, such as IORLW, XORLW and ANDLW
MOVWF TRISC