Datasheet
PIC18F2331/2431/4331/4431
DS39616D-page 94 2010 Microchip Technology Inc.
EXAMPLE 8-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
8.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
8.5.3 UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. The WRERR bit is set when
a write operation is interrupted by a MCLR
Reset, or a
WDT Time-out Reset during normal operation. In these
situations, users can check the WRERR bit and rewrite
the location.
8.6 Flash Program Operation During
Code Protection
See Section 23.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 8-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
PROGRAM_MEMORY
BCF INTCON, GIE ; disable interrupts
MOVLW 55h ; required sequence
MOVWF EECON2 ; write 55h
MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start program (CPU stall)
NOP
BSF INTCON, GIE ; re-enable interrupts
DECFSZ COUNTER_HI ; loop until done
GOTO PROGRAM_LOOP
BCF EECON1, WREN ; disable write to memory
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
TBLPTRU
— —bit 21
(1)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 54
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 54
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 54
TABLAT Program Memory Table Latch 54
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54
EECON2 EEPROM Control Register 2 (not a physical register) 56
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 56
IPR2 OSCFIP
— — EEIP —LVDIP — CCP2IP 57
PIR2 OSCFIF
— — EEIF —LVDIF— CCP2IF 57
PIE2 OSCFIE
— — EEIE —LVDIE — CCP2IE 57
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.