Datasheet

PIC18F2331/2431/4331/4431
DS39616D-page 72  2010 Microchip Technology Inc.
EEADR EEPROM Address Register 0000 0000
EEDATA EEPROM Data Register 0000 0000
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000
EECON1 EEPGD CFGS
— FREE WRERR WREN WR RD xx-0 x000
IPR3
— — — PTIP IC3DRIP IC2QEIP IC1IP TMR5IP ---1 1111
PIR3
— — — PTIF IC3DRIF IC2QEIF IC1IF TMR5IF ---0 0000
PIE3
— — — PTIE IC3DRIE IC2QEIE IC1IE TMR5IE ---0 0000
IPR2 OSCFIP
— —EEIP—LVDIP— CCP2IP 1--1 -1-1
PIR2 OSCFIF
— — EEIF —LVDIF— CCP2IF 0--0 -0-0
PIE2 OSCFIE
— —EEIE—LVDIE— CCP2IE 0--0 -0-0
IPR1
— ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP -111 1111
PIR1
— ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000
PIE1
— ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000
OSCTUNE
— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000
ADCON3 ADRS1 ADRS0
— SSRC4 SSRC3 SSRC2 SSRC1 SSRC0 00-0 0000
ADCHS GDSEL1 GDSEL0 GBSEL1 GBSEL0 GCSEL1 GCSEL0 GASEL1 GASEL0 0000 0000
TRISE
(4)
— — — — — PORTE Data Direction Register
(4)
---- -111
TRISD
(4)
PORTD Data Direction Register 1111 1111
TRISC PORTC Data Direction Register 1111 1111
TRISB PORTB Data Direction Register 1111 1111
TRISA TRISA7
(2)
TRISA6
(1)
PORTA Data Direction Register 1111 1111
PR5H Timer5 Period Register High Byte 1111 1111
PR5L Timer5 Period Register Low Byte 1111 1111
LATE
(4)
— — — — — LATE Data Output Register ---- -xxx
LATD
(4)
LATD Data Output Register xxxx xxxx
LATC LATC Data Output Register xxxx xxxx
LATB LATB Data Output Register xxxx xxxx
LATA LATA7
(2)
LATA6
(1)
LATA Data Output Register xxxx xxxx
TMR5H Timer5 Register High Byte xxxx xxxx
TMR5L Timer5 Register Low Byte xxxx xxxx
PORTE
— — — —RE3
(4,5)
RE2
(4)
RE1
(4)
RE0
(4)
---- xxxx
PORTD
(4)
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx
PORTA RA7
(2)
RA6
(1)
RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000
PTCON0 PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 0000 0000
PTCON1 PTEN PTDIR
— — — — — — 00-- ----
PTMRL PWM Time Base Register (lower 8 bits) 0000 0000
PTMRH
UNUSED PWM Time Base Register (upper 4 bits) ---- 0000
PTPERL PWM Time Base Period Register (lower 8 bits) 1111 1111
PTPERH
UNUSED PWM Time Base Period Register (upper 4 bits) ---- 1111
TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented.
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read
‘0’ in all other oscillator modes.
2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’.
5: The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3
reads ‘0’. This bit is read-only.