Datasheet

PIC18F2331/2431/4331/4431
DS39616D-page 4  2010 Microchip Technology Inc.
Pin Diagrams
28-Pin SPDIP, SOIC
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/V
REF-/CAP1/INDX
RA3/AN3/V
REF+/CAP2/QEA
RA4/AN4/CAP3/QEB
AV
DD
AVSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2/FLTA
RC2/CCP1
RC3/T0CKI/T5CKI/INT0
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PWM4/PGM
RB4/KBI0/PWM5
RB3/PWM3
RB2/PWM2
RB1/PWM1
RB0/PWM0
V
DD
VSS
RC7/RX/DT/SDO
RC6/TX/CK/SS
RC5/INT2/SCK/SCL
RC4/INT1/SDI/SDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIC18F2331/2431
28-Pin QFN
(1)
PIC18F2331
2
3
6
1
18
19
20
21
15
7
16
17
RC0/T1OSO/T1CKI
5
4
RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PWM4/PGM RB4/KBI0/PWM5
RB3/PWM3
RB2/PWM2
RB1/PWM1
RB0/PWM0
V
DD
VSS
RC7/RX/DT/SDO
RC6/TX/CK/SS
RC5/INT2/SCK/SCL
RC4/INT1/SDI/SDA
RA0/AN0 RA1/AN1
RA2/AN2/VREF-/CAP1/INDX
RA3/AN3/V
REF+/CAP2/QEA
RA4/AN4/CAP3/QEB
AV
DD
AVSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC1/T1OSI/CCP2/FLTA
RC2/CCP1
RC3/T0CKI/T5CKI/INT0
10 11 12 13 14
8 9
22
23 24 25 26 27 28
PIC18F2431
MCLR/VPP
Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.