Datasheet

 2010 Microchip Technology Inc. DS39616D-page 299
PIC18F2331/2431/4331/4431
CLRF Clear f
Syntax: [ label ] CLRF f [,a]
Operands: 0  f  255
a [0,1]
Operation: 000h  f,
1  Z
Status Affected: Z
Encoding: 0110 101a ffff ffff
Description: Clears the contents of the specified reg-
ister. If ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If
‘a’ = 1, then the bank will be selected as
per the BSR value.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
CLRF FLAG_REG
Before Instruction
FLAG_REG = 0x5A
After Instruction
FLAG_REG = 0x00
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 000h  WDT,
000h  WDT postscaler,
1  TO,
1  PD
Status Affected: TO, PD
Encoding: 0000 0000 0000 0100
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets the post-
scaler of the WDT. Status bits TO
and
PD
are set.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
Process
Data
No
operation
Example:
CLRWDT
Before Instruction
WDT Counter = ?
After Instruction
WDT Counter = 0x00
WDT Postscaler = 0
TO
=1
PD
=1