Datasheet
PIC18F2331/2431/4331/4431
DS39616D-page 176 2010 Microchip Technology Inc.
18.1 Control Registers
The operation of the PWM module is controlled by a
total of 22 registers. Eight of these are used to
configure the features of the module:
• PWM Timer Control Register 0 (PTCON0)
• PWM Timer Control Register 1 (PTCON1)
• PWM Control Register 0 (PWMCON0)
• PWM Control Register 1 (PWMCON1)
• Dead-Time Control Register (DTCON)
• Output Override Control Register (OVDCOND)
• Output State Register (OVDCONS)
• Fault Configuration Register (FLTCONFIG)
There are also 14 registers that are configured as
seven register pairs of 16 bits. These are used for the
configuration values of specific features. They are:
• PWM Time Base Registers (PTMRH and PTMRL)
• PWM Time Base Period Registers (PTPERH and
PTPERL)
• PWM Special Event Trigger Compare Registers
(SEVTCMPH and SEVTCMPL)
• PWM Duty Cycle #0 Registers
(PDC0H and PDC0L)
• PWM Duty Cycle #1 Registers
(PDC1H and PDC1L)
• PWM Duty Cycle #2 Registers
(PDC2H and PDC2L)
• PWM Duty Cycle #3 Registers
(PDC3H and PDC3L)
All of these register pairs are double-buffered.
18.2 Module Functionality
The PWM module supports several modes of operation
that are beneficial for specific power and motor control
applications. Each mode of operation is described in
subsequent sections.
The PWM module is composed of several functional
blocks. The operation of each is explained separately
in relation to the several modes of operation:
•PWM Time Base
• PWM Time Base Interrupts
•PWM Period
• PWM Duty Cycle
• Dead-Time Generators
• PWM Output Overrides
• PWM Fault Inputs
• PWM Special Event Trigger
18.3 PWM Time Base
The PWM time base is provided by a 12-bit timer with
prescaler and postscaler functions. A simplified block
diagram of the PWM time base is shown in Figure 18-4.
The PWM time base is configured through the
PTCON0 and PTCON1 registers. The time base is
enabled or disabled by respectively setting or clearing
the PTEN bit in the PTCON1 register.
Note: The PTMR register pair (PTMRL:PTMRH)
is not cleared when the PTEN bit is
cleared in software.