Datasheet
Table Of Contents
- Power-Managed Modes:
- Flexible Oscillator Structure:
- Peripheral Highlights:
- Peripheral Highlights (Continued):
- Special Microcontroller Features:
- Pin Diagrams
- Pin Diagrams (Continued)
- Pin Diagrams (Continued)
- Table of Contents
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 Device Overview
- 2.0 Guidelines for Getting Started with PIC18F Microcontrollers
- 3.0 Oscillator Configurations
- 4.0 Power-Managed Modes
- 5.0 Reset
- 5.1 RCON Register
- 5.2 Master Clear (MCLR)
- 5.3 Power-on Reset (POR)
- 5.4 Brown-out Reset (BOR)
- 5.5 Device Reset Timers
- 5.5.1 Power-up Timer (PWRT)
- 5.5.2 Oscillator Start-up Timer (OST)
- 5.5.3 PLL Lock Time-out
- 5.5.4 Time-out Sequence
- TABLE 5-2: Time-out in Various Situations
- FIGURE 5-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)
- FIGURE 5-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 1
- FIGURE 5-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 2
- FIGURE 5-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)
- FIGURE 5-7: Time-out Sequence on POR w/PLL Enabled (MCLR Tied to Vdd)
- 5.6 Reset State of Registers
- 6.0 Memory Organization
- 6.1 Program Memory Organization
- 6.2 PIC18 Instruction Cycle
- 6.3 Data Memory Organization
- 6.4 Data Addressing Modes
- 6.5 Data Memory and the Extended Instruction Set
- 6.6 PIC18 Instruction Execution and the Extended Instruction Set
- 7.0 Flash Program Memory
- 7.1 Table Reads and Table Writes
- 7.2 Control Registers
- 7.3 Reading the Flash Program Memory
- 7.4 Erasing Flash Program Memory
- 7.5 Writing to Flash Program Memory
- 7.6 Flash Program Operation During Code Protection
- 8.0 Data EEPROM Memory
- 9.0 8 X 8 Hardware Multiplier
- 9.1 Introduction
- 9.2 Operation
- EXAMPLE 9-1: 8 x 8 Unsigned Multiply Routine
- EXAMPLE 9-2: 8 x 8 Signed Multiply Routine
- TABLE 9-1: Performance Comparison for Various Multiply Operations
- EQUATION 9-1: 16 x 16 Unsigned Multiplication Algorithm
- EXAMPLE 9-3: 16 x 16 Unsigned Multiply Routine
- EQUATION 9-2: 16 x 16 Signed Multiplication Algorithm
- EXAMPLE 9-4: 16 x 16 Signed Multiply Routine
- 10.0 Interrupts
- 11.0 I/O Ports
- 12.0 Timer0 Module
- 13.0 Timer1 Module
- 14.0 Timer2 Module
- 15.0 Timer3 Module
- 16.0 Capture/Compare/PWM (CCP) Modules
- Register 16-1: CCPxCON Register (CCP2 Module, CCP1 Module in 28-pin Devices)
- 16.1 CCP Module Configuration
- 16.2 Capture Mode
- 16.3 Compare Mode
- 16.4 PWM Mode
- 17.0 Enhanced Capture/ Compare/PWM (ECCP) Module
- Register 17-1: CCP1CON Register (ECCP1 Module, 40/44-pin Devices)
- 17.1 ECCP Outputs and Configuration
- 17.2 Capture and Compare Modes
- 17.3 Standard PWM Mode
- 17.4 Enhanced PWM Mode
- 17.4.1 PWM Period
- 17.4.2 PWM Duty Cycle
- 17.4.3 PWM Output Configurations
- 17.4.4 Half-Bridge Mode
- 17.4.5 Full-Bridge Mode
- 17.4.6 Programmable Dead-Band Delay
- 17.4.7 Enhanced PWM Auto-Shutdown
- 17.4.8 Start-up Considerations
- 17.4.9 Setup for PWM Operation
- 17.4.10 Operation in Power-Managed Modes
- 17.4.11 Effects of a Reset
- 18.0 Master Synchronous Serial Port (MSSP) Module
- 18.1 Master SSP (MSSP) Module Overview
- 18.2 Control Registers
- 18.3 SPI Mode
- 18.4 I2C Mode
- FIGURE 18-7: MSSP Block Diagram (I2C™ Mode)
- 18.4.1 Registers
- 18.4.2 Operation
- 18.4.3 Slave Mode
- EXAMPLE 18-2: Address Masking
- FIGURE 18-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-Bit Addressing)
- FIGURE 18-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Addressing)
- FIGURE 18-10: I2C™ Slave Mode Timing (Transmission, 7-Bit Addressing)
- FIGURE 18-11: I2C™ Slave Mode Timing with SEN = 0 and ADMSK = 01001 (Reception, 10-bit Addressing)
- FIGURE 18-12: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-Bit Addressing)
- FIGURE 18-13: I2C™ Slave Mode Timing (Transmission, 10-Bit Addressing)
- 18.4.4 Clock Stretching
- 18.4.5 General Call Address Support
- 18.4.6 Master Mode
- 18.4.7 Baud Rate
- 18.4.8 I2C Master Mode Start Condition Timing
- 18.4.9 I2C Master Mode Repeated Start Condition Timing
- 18.4.10 I2C Master Mode Transmission
- 18.4.11 I2C Master Mode Reception
- 18.4.12 Acknowledge Sequence Timing
- 18.4.13 Stop Condition Timing
- 18.4.14 Sleep Operation
- 18.4.15 Effects of a Reset
- 18.4.16 Multi-Master Mode
- 18.4.17 Multi -Master Communication, Bus Collision and Bus Arbitration
- FIGURE 18-27: Bus Collision Timing for Transmit and Acknowledge
- FIGURE 18-28: Bus Collision During Start Condition (SDA Only)
- FIGURE 18-29: Bus Collision During Start Condition (SCL = 0)
- FIGURE 18-30: BRG Reset Due to SDA Arbitration During Start Condition
- FIGURE 18-31: Bus Collision During a Repeated Start Condition (Case 1)
- FIGURE 18-32: Bus Collision During Repeated Start Condition (Case 2)
- FIGURE 18-33: Bus Collision During a Stop Condition (Case 1)
- FIGURE 18-34: Bus Collision During a Stop Condition (Case 2)
- TABLE 18-4: Registers Associated with I2C™ Operation
- 19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- Register 19-1: TXSTA: Transmit Status And Control Register
- Register 19-2: RCSTA: Receive Status And Control Register
- Register 19-3: BAUDCON: Baud Rate Control Register
- 19.1 Baud Rate Generator (BRG)
- 19.2 EUSART Asynchronous Mode
- 19.3 EUSART Synchronous Master Mode
- 19.4 EUSART Synchronous Slave Mode
- 20.0 10-Bit Analog-to-Digital Converter (A/D) Module
- Register 20-1: ADCON0: A/D Control Register 0
- Register 20-2: ADCON1: A/D Control Register 1
- Register 20-3: ADCON2: A/D Control Register 2
- FIGURE 20-1: A/D Block Diagram
- FIGURE 20-2: A/D Transfer Function
- FIGURE 20-3: Analog Input Model
- 20.1 A/D Acquisition Requirements
- 20.2 Selecting and Configuring Acquisition Time
- 20.3 Selecting the A/D Conversion Clock
- 20.4 Operation in Power-Managed Modes
- 20.5 Configuring Analog Port Pins
- 20.6 A/D Conversions
- 20.7 Discharge
- 20.8 Use of the CCP2 Trigger
- 21.0 Comparator Module
- Register 21-1: CMCON: Comparator Control Register
- 21.1 Comparator Configuration
- 21.2 Comparator Operation
- 21.3 Comparator Reference
- 21.4 Comparator Response Time
- 21.5 Comparator Outputs
- 21.6 Comparator Interrupts
- 21.7 Comparator Operation During Sleep
- 21.8 Effects of a Reset
- 21.9 Analog Input Connection Considerations
- 22.0 Comparator Voltage Reference Module
- 23.0 High/Low-Voltage Detect (HLVD)
- 24.0 Special Features of the CPU
- 24.1 Configuration Bits
- TABLE 24-1: Configuration Bits and Device IDs
- Register 24-1: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)
- Register 24-2: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)
- Register 24-3: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)
- Register 24-4: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)
- Register 24-5: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)
- Register 24-6: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h)
- Register 24-7: CONFIG5H: Configuration Register 5 High (Byte Address 300009h)
- Register 24-8: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah)
- Register 24-9: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh)
- Register 24-10: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch)
- Register 24-11: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh)
- Register 24-12: DEVID1: Device ID Register 1 for PIC18F2221/2321/4221/4321 Devices
- Register 24-13: DEVID2: Device ID Register 2 for PIC18F2221/2321/4221/4321 Devices
- 24.2 Watchdog Timer (WDT)
- 24.3 Two-Speed Start-up
- 24.4 Fail-Safe Clock Monitor
- 24.5 Program Verification and Code Protection
- 24.6 ID Locations
- 24.7 In-Circuit Serial Programming
- 24.8 In-Circuit Debugger
- 24.9 Single-Supply ICSP Programming
- 24.1 Configuration Bits
- 25.0 Instruction Set Summary
- 25.1 Standard Instruction Set
- 25.2 Extended Instruction Set
- 26.0 Development Support
- 27.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 27.1 DC Characteristics: Supply Voltage PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial)
- 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial)
- 27.3 DC Characteristics: PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial)
- 27.4 AC (Timing) Characteristics
- 27.4.1 Timing Parameter Symbology
- 27.4.2 Timing Conditions
- 27.4.3 Timing Diagrams and Specifications
- FIGURE 27-6: External Clock Timing (All Modes Except PLL)
- TABLE 27-6: External Clock Timing Requirements
- TABLE 27-7: PLL Clock Timing Specifications (Vdd = 4.2V to 5.5V)
- TABLE 27-8: AC Characteristics: Internal RC Accuracy
- FIGURE 27-7: CLKO and I/O Timing
- TABLE 27-9: CLKO and I/O Timing Requirements
- FIGURE 27-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
- FIGURE 27-9: Brown-out Reset Timing
- TABLE 27-10: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements
- FIGURE 27-10: Timer0 and Timer1 External Clock Timings
- TABLE 27-11: Timer0 and Timer1 External Clock Requirements
- FIGURE 27-11: Capture/Compare/PWM Timings (All CCP Modules)
- TABLE 27-12: Capture/Compare/PWM Requirements (All CCP Modules)
- FIGURE 27-12: Parallel Slave Port Timing (PIC18F4221/4321)
- TABLE 27-13: Parallel Slave Port Requirements (PIC18F4221/4321)
- FIGURE 27-13: Example SPI Master Mode Timing (CKE = 0)
- TABLE 27-14: Example SPI Mode Requirements (Master Mode, CKE = 0)
- FIGURE 27-14: Example SPI Master Mode Timing (CKE = 1)
- TABLE 27-15: Example SPI Mode Requirements (Master Mode, CKE = 1)
- FIGURE 27-15: Example SPI Slave Mode Timing (CKE = 0)
- TABLE 27-16: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)
- FIGURE 27-16: Example SPI Slave Mode Timing (CKE = 1)
- TABLE 27-17: Example SPI Slave Mode Requirements (CKE = 1)
- FIGURE 27-17: I2C™ Bus Start/Stop Bits Timing
- TABLE 27-18: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)
- FIGURE 27-18: I2C™ Bus Data Timing
- TABLE 27-19: I2C™ Bus Data Requirements (Slave Mode)
- FIGURE 27-19: Master SSP I2C™ Bus Start/Stop Bits Timing Waveforms
- TABLE 27-20: Master SSP I2C™ Bus Start/Stop Bits Requirements
- FIGURE 27-20: Master SSP I2C™ Bus Data Timing
- TABLE 27-21: Master SSP I2C™ Bus Data Requirements
- FIGURE 27-21: EUSART Synchronous Transmission (Master/slave) Timing
- TABLE 27-22: EUSART Synchronous Transmission Requirements
- FIGURE 27-22: EUSART Synchronous Receive (Master/Slave) Timing
- TABLE 27-23: EUSART Synchronous Receive Requirements
- TABLE 27-24: A/D Converter Characteristics
- FIGURE 27-23: A/D Conversion Timing
- TABLE 27-25: A/D Conversion Requirements
- 28.0 Packaging Information
- Appendix A: Revision History
- Appendix B: Device Differences
- Appendix C: Conversion Considerations
- Appendix D: Migration from Baseline to Enhanced Devices
- Appendix E: Migration From Mid-Range to Enhanced Devices
- Appendix F: Migration From High-End to Enhanced Devices
- INDEX
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Reader Response
- PIC18F2221/2321/4221/4321 Product Identification System
- Worldwide Sales and Service
© 2009 Microchip Technology Inc. DS39689F-page 77
PIC18F2221/2321/4221/4321 FAMILY
6.5.3 MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET
ADDRESSING MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the first 96 locations of Access
RAM (00h to 5Fh) are mapped. Rather than containing
just the contents of the bottom half of Bank 0, this mode
maps the contents from Bank 0 and a user-defined
“window” that can be located anywhere in the data
memory space. The value of FSR2 establishes the
lower boundary of the addresses mapped into the
window, while the upper boundary is defined by FSR2
plus 95 (5Fh). Addresses in the Access RAM above
5Fh are mapped as previously described (see
Section 6.3.2 “Access Bank”). An example of Access
Bank remapping in this addressing mode is shown in
Figure 6-9.
Remapping of the Access Bank applies only to opera-
tions using the Indexed Literal Offset Addressing
mode. Operations that use the BSR (Access RAM bit is
‘1’) will continue to use direct addressing as before.
6.6 PIC18 Instruction Execution and
the Extended Instruction Set
Enabling the extended instruction set adds eight
additional commands to the existing PIC18 instruction
set. These instructions are executed as described in
Section 24.2 “Extended Instruction Set”.
FIGURE 6-9: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET
ADDRESSING MODE
Data Memory
000h
100h
200h
F80h
F00h
FFFh
Bank 1
Bank 15
Bank 2
through
Bank 14
SFRs
05Fh
ADDWF f, d, a
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 Pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
Locations in Bank 0, from
060h to 07Fh, are mapped
as usual to the middle of
the Access Bank.
Special Function Regis-
ters at F80h through FFFh
are mapped to 80h
through FFh, as usual.
Bank 0 addresses below
5Fh can still be addressed
by using the BSR.
Access Bank
00h
80h
FFh
7Fh
Bank 0
SFRs
Bank 1 “Window”
Bank 0
Bank 0
Window
Example Situation:
07Fh
120h
17Fh
5Fh
Bank 1