Datasheet

© 2009 Microchip Technology Inc. DS39689F-page 363
PIC18F2221/2321/4221/4321 FAMILY
FIGURE 27-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol Characteristic Min Max Units Conditions
70 TssL2scH,
Tss L2s cL
SS
↓ to SCK ↓ or SCK ↑ Input 3 TCY —ns
71 TscH SCK Input High Time Continuous 1.25 T
CY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 TscL SCK Input Low Time Continuous 1.25 T
CY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 TdiV2scH,
TdiV2scL
Setup Time of SDI Data Input to SCK Edge 20 — ns
73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 T
CY + 40 — ns (Note 2)
74 TscH2diL,
Tsc L2d iL
Hold Time of SDI Data Input to SCK Edge 40 — ns
75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns
PIC18LFXXXX 45 ns V
DD = 2.0V
76 TdoF SDO Data Output Fall Time — 25 ns
77 TssH2doZ SS
↑ to SDO Output High-Impedance 10 50 ns
80 TscH2doV,
TscL2doV
SDO Data Output Valid after SCK Edge PIC18FXXXX — 50 ns
PIC18LFXXXX 100 ns VDD = 2.0V
83 TscH2ssH,
Tsc L2s sH
SS
↑ after SCK edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73
74
75, 76
77
80
MSb LSb
bit 6 - - - - - -1
bit 6 - - - -1 LSb In
83
MSb In