Datasheet

© 2009 Microchip Technology Inc. DS39689F-page 247
PIC18F2221/2321/4221/4321 FAMILY
21.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 21-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
V
SS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
FIGURE 21-4: COMPARATOR ANALOG INPUT MODEL
TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 57
CVRCON CVREN CVROE CVRR
CVRSS CVR3 CVR2 CVR1 CVR0 57
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 58
PIR2
OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 58
PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 58
IPR2
OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 58
PORTA RA7
(1)
RA6
(1)
RA5 RA4 RA3 RA2 RA1 RA0 58
LATA LATA7
(1)
LATA6
(1)
PORTA Data Latch Register (Read and Write to Data Latch) 58
TRISA TRISA7
(1)
TRISA6
(1)
PORTA Data Direction Control Register 58
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: PORTA<7:6> and their direction and latch bits are individually configured as port pins based on various
primary oscillator modes. When disabled, these bits read as ‘0’.
VA
R
S < 10k
A
IN
CPIN
5 pF
V
DD
VT = 0.6V
VT = 0.6V
RIC
ILEAKAGE
±100 nA
V
SS
Legend: CPIN = Input Capacitance
V
T = Threshold Voltage
I
LEAKAGE = Leakage Current at the pin due to various junctions
R
IC = Interconnect Resistance
R
S = Source Impedance
VA = Analog Voltage
Comparator
Input