Datasheet

© 2009 Microchip Technology Inc. DS39689F-page 221
PIC18F2221/2321/4221/4321 FAMILY
19.2 EUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ)
format (one Start bit, eight or nine data bits and one
Stop bit). The most common data format is 8 bits. An
on-chip dedicated 8-bit/16-bit Baud Rate Generator
can be used to derive standard baud rate frequencies
from the oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. The Baud Rate Generator produces a clock, either
x16 or x64 of the bit shift rate depending on the BRGH
and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity
is not supported by the hardware but can be
implemented in software and stored as the 9th data bit.
The TXCKP (BAUDCON<4>) and RXDTP
(BAUDCON<5>) bits allow the TX and RX signals to be
inverted (polarity reversed). Devices that buffer signals
between TTL and RS-232 levels also invert the signal.
Setting the TXCKP and RXDTP bits allows for the use of
circuits that provide buffering without inverting the signal.
In Asynchronous mode, clock polarity is selected with
the TXCKP bit (BAUDCON<4>). Setting TXCKP sets
the Idle state on CK as high, while clearing the bit sets
the Idle state as low. Data polarity is selected with the
RXDTP bit (BAUDCON<5>). Setting RXDTP inverts
data on RX, while clearing the bit has no affect on
received data.
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto-Wake-up on Break signal
• 12-bit Break Character Transmit
• Auto-Baud Rate Detection
• Pin State Polarity
19.2.1 EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 19-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
Once the TXREG register transfers the data to the TSR
register (occurs in one T
CY), the TXREG register is empty
and the TXIF flag bit (PIR1<4>) is set. This interrupt can
be enabled or disabled by setting or clearing the interrupt
enable bit, TXIE (PIE1<4>). TXIF will be set regardless of
the state of TXIE; it cannot be cleared in software. TXIF
is also not cleared immediately upon loading TXREG, but
becomes valid in the second instruction cycle following
the load instruction. Polling TXIF immediately following a
load of TXREG will return invalid results.
While TXIF indicates the status of the TXREG register,
another bit, TRMT (TXSTA<1>), shows the status of
the TSR register. TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit so the user has to poll this bit in order to
determine if the TSR register is empty.
The TXCKP bit (BAUDCON<4>) allows the TX signal to
be inverted (polarity reversed). Devices that buffer
signals from TTL to RS-232 levels also invert the signal
(when TTL = 1, RS-232 = negative). Inverting the
polarity of the TX pin data by setting the TXCKP bit
allows for use of circuits that provide buffering without
inverting the signal.
To set up an Asynchronous Transmission:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
3. If the signal from the TX pin is to be inverted, set
the TXCKP bit.
4. If interrupts are desired, set enable bit, TXIE.
5. If 9-bit transmission is desired, set transmit bit,
TX9; can be used as address/data bit.
6. Enable the transmission by setting bit, TXEN,
which will also set bit, TXIF.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
8. Load data to the TXREG register (starts
transmission).
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set.