Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SSOP 28 8-Bit 40 MHz I/O number 25

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Table Of Contents

Power-Managed Modes:
Flexible Oscillator Structure:
Peripheral Highlights:
Peripheral Highlights (Continued):
Special Microcontroller Features:
Pin Diagrams
Pin Diagrams (Continued)
Pin Diagrams (Continued)
Table of Contents
Most Current Data Sheet
Errata
Customer Notification System
1.0 Device Overview
- 1.1 New Core Features
  - 1.1.1 nanoWatt Technology
  - 1.1.2 Multiple Oscillator Options and Features
- 1.2 Other Special Features
- 1.3 Details on Individual Family Members
2.0 Guidelines for Getting Started with PIC18F Microcontrollers
- 2.1 Basic Connection Requirements
  - FIGURE 2-1: Recommended Minimum connections
- 2.2 Power Supply Pins
  - 2.2.1 Decoupling Capacitors
  - 2.2.2 Tank Capacitors
- 2.3 Master Clear (MCLR) Pin
  - FIGURE 2-2: Example of MCLR Pin Connections
- 2.4 ICSP Pins
- 2.5 External Oscillator Pins
  - FIGURE 2-3: Suggested Placement of the Oscillator Circuit
- 2.6 Unused I/Os
3.0 Oscillator Configurations
- 3.1 Oscillator Types
- 3.2 Crystal Oscillator/Ceramic Resonators
- 3.3 External Clock Input
  - FIGURE 3-3: External Clock Input Operation (EC Configuration)
  - FIGURE 3-4: External Clock Input Operation (ECIO Configuration)
- 3.4 RC Oscillator
  - FIGURE 3-5: RC Oscillator Mode
  - FIGURE 3-6: RCIO Oscillator Mode
- 3.5 PLL Frequency Multiplier
  - 3.5.1 HSPLL Oscillator Mode
    - FIGURE 3-7: HSPLL Block Diagram
  - 3.5.2 PLL and INTOSC
- 3.6 Internal Oscillator Block
- 3.7 Clock Sources and Oscillator Switching
- 3.8 Effects of Power-Managed Modes on the Various Clock Sources
- 3.9 Power-up Delays
  - 3.9.1 Delays for Power-up and Return to Primary Clock
    - TABLE 3-3: OSC1 and OSC2 Pin States in Sleep Mode
4.0 Power-Managed Modes
- 4.1 Selecting Power-Managed Modes
- 4.2 Run Modes
- 4.3 Sleep Mode
- 4.4 Idle Modes
- 4.5 Exiting Idle and Sleep Modes
5.0 Reset
- 5.1 RCON Register
  - FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit
  - Register 5-1: RCON: Reset Control Register
- 5.2 Master Clear (MCLR)
- 5.3 Power-on Reset (POR)
  - FIGURE 5-2: External Power-on Reset Circuit (for Slow Vdd Power-up)
- 5.4 Brown-out Reset (BOR)
- 5.5 Device Reset Timers
- 5.6 Reset State of Registers
  - TABLE 5-3: Status Bits, Their Significance and the Initialization Condition for RCON Register
  - TABLE 5-4: Initialization Conditions for All Registers
6.0 Memory Organization
- 6.1 Program Memory Organization
- 6.2 PIC18 Instruction Cycle
- 6.3 Data Memory Organization
- 6.4 Data Addressing Modes
- 6.5 Data Memory and the Extended Instruction Set
- 6.6 PIC18 Instruction Execution and the Extended Instruction Set
  - FIGURE 6-9: Remapping the Access Bank with Indexed Literal Offset Addressing Mode
7.0 Flash Program Memory
- 7.1 Table Reads and Table Writes
  - FIGURE 7-1: Table Read Operation
  - FIGURE 7-2: Table Write Operation
- 7.2 Control Registers
- 7.3 Reading the Flash Program Memory
  - FIGURE 7-4: Reads From Flash Program Memory
  - EXAMPLE 7-1: Reading a Flash Program Memory Word
- 7.4 Erasing Flash Program Memory
  - 7.4.1 Flash Program Memory Erase Sequence
    - EXAMPLE 7-2: Erasing a Flash Program Memory Row
- 7.5 Writing to Flash Program Memory
- 7.6 Flash Program Operation During Code Protection
  - TABLE 7-2: Registers Associated with Program Flash Memory
8.0 Data EEPROM Memory
- 8.1 EECON1 and EECON2 Registers
  - Register 8-1: EECON1: Data EEPROM Control Register 1
- 8.2 Reading the Data EEPROM Memory
- 8.3 Writing to the Data EEPROM Memory
- 8.4 Write Verify
  - EXAMPLE 8-1: Data EEPROM Read
  - EXAMPLE 8-2: Data EEPROM Write
- 8.5 Operation During Code-Protect
- 8.6 Protection Against Spurious Write
- 8.7 Using the Data EEPROM
  - EXAMPLE 8-3: Data EEPROM Refresh Routine
  - TABLE 8-1: Registers Associated with Data EEPROM Memory
9.0 8 X 8 Hardware Multiplier
- 9.1 Introduction
- 9.2 Operation
10.0 Interrupts
- FIGURE 10-1: PIC18 Interrupt Logic
- 10.1 INTCON Registers
- 10.2 PIR Registers
  - Register 10-4: PIR1: Peripheral Interrupt Request (Flag) Register 1
  - Register 10-5: PIR2: Peripheral Interrupt Request (Flag) Register 2
- 10.3 PIE Registers
  - Register 10-6: PIE1: Peripheral Interrupt Enable Register 1
  - Register 10-7: PIE2: Peripheral Interrupt Enable Register 2
- 10.4 IPR Registers
  - Register 10-8: IPR1: Peripheral Interrupt Priority Register 1
  - Register 10-9: IPR2: Peripheral Interrupt Priority Register 2
- 10.5 RCON Register
  - Register 10-10: RCON: Reset Control Register
- 10.6 INTx Pin Interrupts
- 10.7 TMR0 Interrupt
- 10.8 PORTB Interrupt-on-Change
- 10.9 Context Saving During Interrupts
  - EXAMPLE 10-1: Saving STATUS, WREG and BSR Registers in RAM
11.0 I/O Ports
- FIGURE 11-1: Generic I/O Port Operation
- 11.1 PORTA, TRISA and LATA Registers
- 11.2 PORTB, TRISB and LATB Registers
- 11.3 PORTC, TRISC and LATC Registers
- 11.4 PORTD, TRISD and LATD Registers
- 11.5 PORTE, TRISE and LATE Registers
  - EXAMPLE 11-5: Initializing PORTE
  - 11.5.1 PORTE in 28-Pin Devices
- 11.6 Parallel Slave Port
12.0 Timer0 Module
- Register 12-1: T0CON: Timer0 Control Register
- 12.1 Timer0 Operation
- 12.2 Timer0 Reads and Writes in 16-Bit Mode
  - FIGURE 12-1: Timer0 Block Diagram (8-Bit Mode)
  - FIGURE 12-2: Timer0 Block Diagram (16-Bit Mode)
- 12.3 Prescaler
  - 12.3.1 Switching Prescaler Assignment
- 12.4 Timer0 Interrupt
  - TABLE 12-1: Registers Associated with Timer0
13.0 Timer1 Module
- Register 13-1: T1CON: Timer1 Control Register
- 13.1 Timer1 Operation
  - FIGURE 13-1: Timer1 Block Diagram
  - FIGURE 13-2: Timer1 Block Diagram (16-Bit Read/Write Mode)
- 13.2 Timer1 16-Bit Read/Write Mode
- 13.3 Timer1 Oscillator
- 13.4 Timer1 Interrupt
- 13.5 Resetting Timer1 Using the CCP Special Event Trigger
- 13.6 Using Timer1 as a Real-Time Clock
  - EXAMPLE 13-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service
  - TABLE 13-2: Registers Associated with Timer1 as a Timer/Counter
14.0 Timer2 Module
- 14.1 Timer2 Operation
  - Register 14-1: T2CON: Timer2 Control Register
- 14.2 Timer2 Interrupt
- 14.3 Timer2 Output
  - FIGURE 14-1: Timer2 Block Diagram
  - TABLE 14-1: Registers Associated with Timer2 as a Timer/Counter
15.0 Timer3 Module
- Register 15-1: T3CON: Timer3 Control Register
- 15.1 Timer3 Operation
  - FIGURE 15-1: Timer3 Block Diagram (8-Bit Read/Write Mode)
  - FIGURE 15-2: Timer3 Block Diagram (16-Bit Read/Write Mode)
- 15.2 Timer3 16-Bit Read/Write Mode
- 15.3 Using the Timer1 Oscillator as the Timer3 Clock Source
- 15.4 Timer3 Interrupt
- 15.5 Resetting Timer3 Using the CCP Special Event Trigger
  - TABLE 15-1: Registers Associated with Timer3 as a Timer/Counter
16.0 Capture/Compare/PWM (CCP) Modules
- Register 16-1: CCPxCON Register (CCP2 Module, CCP1 Module in 28-pin Devices)
- 16.1 CCP Module Configuration
  - 16.1.1 CCP Modules and Timer Resources
    - TABLE 16-1: CCP Mode – Timer Resources
  - 16.1.2 CCP2 Pin Assignment
    - TABLE 16-2: Interactions Between CCP1 and CCP2 for Timer Resources
- 16.2 Capture Mode
- 16.3 Compare Mode
- 16.4 PWM Mode
17.0 Enhanced Capture/ Compare/PWM (ECCP) Module
- Register 17-1: CCP1CON Register (ECCP1 Module, 40/44-pin Devices)
- 17.1 ECCP Outputs and Configuration
  - 17.1.1 ECCP Modules and Timer Resources
- 17.2 Capture and Compare Modes
  - 17.2.1 Special Event Trigger
- 17.3 Standard PWM Mode
  - TABLE 17-1: Pin Assignments for Various ECCP1 Modes
- 17.4 Enhanced PWM Mode
18.0 Master Synchronous Serial Port (MSSP) Module
- 18.1 Master SSP (MSSP) Module Overview
- 18.2 Control Registers
- 18.3 SPI Mode
- 18.4 I2C Mode
19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- Register 19-1: TXSTA: Transmit Status And Control Register
- Register 19-2: RCSTA: Receive Status And Control Register
- Register 19-3: BAUDCON: Baud Rate Control Register
- 19.1 Baud Rate Generator (BRG)
- 19.2 EUSART Asynchronous Mode
- 19.3 EUSART Synchronous Master Mode
  - 19.3.1 EUSART Synchronous Master Transmission
  - 19.3.2 EUSART Synchronous Master Reception
    - FIGURE 19-13: Synchronous Reception (Master Mode, SREN)
    - TABLE 19-8: Registers Associated with Synchronous Master Reception
- 19.4 EUSART Synchronous Slave Mode
  - 19.4.1 EUSART Synchronous Slave Transmission
    - TABLE 19-9: Registers Associated with Synchronous Slave Transmission
  - 19.4.2 EUSART Synchronous Slave Reception
    - TABLE 19-10: Registers Associated with Synchronous Slave Reception
20.0 10-Bit Analog-to-Digital Converter (A/D) Module
- Register 20-1: ADCON0: A/D Control Register 0
- Register 20-2: ADCON1: A/D Control Register 1
- Register 20-3: ADCON2: A/D Control Register 2
- FIGURE 20-1: A/D Block Diagram
- FIGURE 20-2: A/D Transfer Function
- FIGURE 20-3: Analog Input Model
- 20.1 A/D Acquisition Requirements
- 20.2 Selecting and Configuring Acquisition Time
- 20.3 Selecting the A/D Conversion Clock
  - TABLE 20-1: Tad vs. Device Operating Frequencies
- 20.4 Operation in Power-Managed Modes
- 20.5 Configuring Analog Port Pins
- 20.6 A/D Conversions
- 20.7 Discharge
  - FIGURE 20-4: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)
  - FIGURE 20-5: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)
- 20.8 Use of the CCP2 Trigger
  - TABLE 20-2: Registers Associated with A/D Operation
21.0 Comparator Module
- Register 21-1: CMCON: Comparator Control Register
- 21.1 Comparator Configuration
  - FIGURE 21-1: Comparator I/O Operating Modes
- 21.2 Comparator Operation
- 21.3 Comparator Reference
- 21.4 Comparator Response Time
- 21.5 Comparator Outputs
  - FIGURE 21-3: Comparator Output Block Diagram
- 21.6 Comparator Interrupts
- 21.7 Comparator Operation During Sleep
- 21.8 Effects of a Reset
- 21.9 Analog Input Connection Considerations
  - FIGURE 21-4: Comparator Analog Input Model
  - TABLE 21-1: Registers Associated with Comparator Module
22.0 Comparator Voltage Reference Module
- 22.1 Configuring the Comparator Voltage Reference
  - Register 22-1: CVRCON: Comparator Voltage Reference Control Register
  - FIGURE 22-1: Comparator Voltage Reference Block Diagram
- 22.2 Voltage Reference Accuracy/Error
- 22.3 Operation During Sleep
- 22.4 Effects of a Reset
- 22.5 Connection Considerations
  - FIGURE 22-2: Comparator Voltage Reference Output Buffer Example
  - TABLE 22-1: Registers Associated with Comparator Voltage Reference
23.0 High/Low-Voltage Detect (HLVD)
- Register 23-1: HLVDCON: High/Low-Voltage Detect Control Register
- 23.1 Operation
  - FIGURE 23-1: HLVD Module Block Diagram (with External Input)
- 23.2 HLVD Setup
- 23.3 Current Consumption
- 23.4 HLVD Start-up Time
  - FIGURE 23-2: Low-Voltage Detect Operation (VDIRMAG = 0)
  - FIGURE 23-3: High-Voltage Detect Operation (VDIRMAG = 1)
- 23.5 Applications
  - FIGURE 23-4: Typical Low-Voltage Detect Application
- 23.6 Operation During Sleep
- 23.7 Effects of a Reset
  - TABLE 23-1: Registers Associated with High/Low-Voltage Detect Module
24.0 Special Features of the CPU
- 24.1 Configuration Bits
- 24.2 Watchdog Timer (WDT)
  - 24.2.1 Control Register
- 24.3 Two-Speed Start-up
  - 24.3.1 Special Considerations for Using Two-Speed Start-up
    - FIGURE 24-2: Timing Transition for Two-Speed Start-up (INTOSC to HSPLL)
- 24.4 Fail-Safe Clock Monitor
- 24.5 Program Verification and Code Protection
- 24.6 ID Locations
- 24.7 In-Circuit Serial Programming
- 24.8 In-Circuit Debugger
  - TABLE 24-4: Debugger Resources
- 24.9 Single-Supply ICSP Programming
25.0 Instruction Set Summary
- 25.1 Standard Instruction Set
- 25.2 Extended Instruction Set
- 26.0 Development Support
27.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 27.1 DC Characteristics: Supply Voltage PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial)
- 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial)
- 27.3 DC Characteristics: PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial)
- 27.4 AC (Timing) Characteristics
28.0 Packaging Information
- 28.1 Package Marking Information
- 28.1 Package Marking Information (Continued)
Appendix A: Revision History
- Revision A (July 2005)
- Revision B (August 2006)
- Revision C (October 2006)
- Revision D (January 2007)
- Revision E (February 2007)
- Revision F (September 2009)
Appendix B: Device Differences
- TABLE B-1: Device Differences
Appendix C: Conversion Considerations
Appendix D: Migration from Baseline to Enhanced Devices
Appendix E: Migration From Mid-Range to Enhanced Devices
Appendix F: Migration From High-End to Enhanced Devices
INDEX
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PIC18F2221/2321/4221/4321 FAMILY

FIGURE 18-9: I

C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011

(RECEPTION, 7-BIT ADDRESSING)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON1<6>)

12345678912345678912345 789

A7 A6 A5 X A3 X X D7D6 D5D4D3D2D1 D0 D7D6D5D4D3 D1D0

ACK

Receiving Data

ACK

Receiving Data

R/W

= 0

ACK

Receiving Address

Cleared in software

SSPBUF is read

Bus master

terminates

transfer

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

CKP

(CKP does not reset to ‘0’ when SEN = 0)

Note 1: x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).

2: In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt.