Information

© 2008 Microchip Technology Inc. DS80310G-page 11
PIC18F2221/2321/4221/4321
9. Module: EUSART
The descriptions of the RXDTP and TXCKP bits
(BAUDCON<5:4>) are being revised as shown
below (changes in bold).
In this document’s Revision E change, the
Synchronous mode content was removed from the
bit 5 (RXDTP) description.
REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER (EXCERPT)
R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ABDOVF RCIDL RXDTP TXCKP BRG16
— WUE ABDEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 5 RXDTP: Data/Receive Polarity Select bit (Asynchronous mode only)
Asynchronous mode:
1 = Receive data (RX) is inverted (active-low)
0 = Receive data (RX) is not inverted (active-high)
bit 4 TXCKP: Clock and Data Polarity Select bit
Asynchronous mode:
1 = Idle state for transmit (TX) is a low level
0 = Idle state for transmit (TX) is a high level
Synchronous mode:
1 = Idle state for clock (CK) is a high level
0 = Idle state for clock (CK) is a low level