Information

 2010 Microchip Technology Inc. DS80285C-page 3

PIC18F2221/2321/4221/4321

Silicon Errata Issues

1. Module: 10-Bit Analog-to-Digital

Converter (A/D)

When the AD clock source is selected as 2 TOSC

or RC (when ADCS<2:0 = 000 or x11), in

extremely rare cases, the E

IL (Integral Linearity

Error) and E

DL (Differential Linearity Error) may

exceed the data sheet specification at

codes 511 and 512.

Work around

Select the AD clock source as 4 TOSC, 8 TOSC,

16 T

OSC, 32 TOSC or 64 TOSC and avoid

selecting 2 T

OSC or RC.

Affected Silicon Revisions

2. Module: Master Synchronous Serial Port

(MSSP)

When configured for I

C™ slave reception, the

MSSP module may not receive the correct data, in

extremely rare cases. This occurs only if the Serial

Receive/Transmit Buffer Register (SSPBUF) is

not read within a window after the SSPIF interrupt

(PIR1<3>) has occurred.

Work around

The issue can be resolved in either of these ways:

• Prior to the I

C slave reception, enable the

clock stretching feature.

This is done by setting the SEN bit

(SSPCON2<0>).

• Each time the SSPIF is set, read the SSPBUF

before the first rising clock edge of the next byte

being received.

Affected Silicon Revisions

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated by the shaded column in

the following tables apply to the current

silicon revision (B3).

B2 B3