Information

PIC18F2221/2321/4221/4321
DS80285C-page 2  2010 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature
Item
Number
Issue Summary
Affected Revisions
(1)
B2 B3
10-Bit A/D
2TOSC or
RC
1.
When the A/D clock source is set as 2 TOSC
or RC, the Integral Linearity Error and Differ-
ential Linearity Error may exceed the data
sheet specification, in extremely rare cases,
at codes 511 and 512.
XX
MSSP
I
2
C™ Slave
Reception
2.
When configured for I
2
C slave reception, the
MSSP module may not receive the correct
data if the SSPBUF register is not read
within a window after an SSPIF interrupt
occurs
XX
Note 1: Only those issues indicated in the last column apply to the current silicon revision.