Datasheet

PIC18F2221/2321/4221/4321 FAMILY
DS39689F-page 354 © 2009 Microchip Technology Inc.
27.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 27-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
TABLE 27-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No.
Symbol Characteristic Min Max Units Conditions
1A F
OSC External CLKI Frequency
(1)
DC 1 MHz XT, RC Oscillator mode
DC 25 MHz HS Oscillator mode
DC 40 MHz EC Oscillator mode
4 10 MHz HS+PLL Oscillator mode
DC 50 kHz LP Oscillator mode
Oscillator Frequency
(1)
DC 4 MHz RC Oscillator mode
0.1 4 MHz XT Oscillator mode
4 25 MHz HS Oscillator mode
5 200 kHz LP Oscillator mode
1T
OSC External CLKI Period
(1)
1000 — ns XT, RC Oscillator mode
40 — ns HS Oscillator mode
25 — ns EC Oscillator mode
100 250 ns HS+PLL Oscillator mode
32 — μs LP Oscillator mode
Oscillator Period
(1)
250 — ns RC Oscillator mode
250 1 μs XT Oscillator mode
40 250 ns HS Oscillator mode
5209μs LP Oscillator mode
2T
CY Instruction Cycle Time
(1)
100 — ns TCY = 4/FOSC, Industrial
160 — ns T
CY = 4/FOSC, Extended
3T
OSL,
T
OSH
External Clock in (OSC1)
High or Low Time
30 — ns XT Oscillator mode
2.5 — μs LP Oscillator mode
10 — ns HS Oscillator mode
4T
OSR,
T
OSF
External Clock in (OSC1)
Rise or Fall Time
— 20 ns XT Oscillator mode
— 50 ns LP Oscillator mode
— 7.5 ns HS Oscillator mode
Note 1: Instruction cycle period (T
CY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
OSC1
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
1
2
3
3
4
4