Datasheet

© 2009 Microchip Technology Inc. DS39689F-page 275
PIC18F2221/2321/4221/4321 FAMILY
TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS
24.5.1 PROGRAM MEMORY
CODE PROTECTION
The program memory may be read to or written from
any location using the table read and table write
instructions. The device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A
block of user memory may be protected from table
writes if the WRTn Configuration bit is ‘0’. The EBTRn
bits control table reads. For a block of user memory
with the EBTRn bit set to ‘0’, a table read instruction
that executes from within that block is allowed to read.
A table read instruction that executes from a location
outside of that block is not allowed to read and will result
in reading ‘0’s. Figures 24-6 through 24-8 illustrate table
write and table read protection.
FIGURE 24-6: TABLE WRITE (WRTn) DISALLOWED
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
300008h CONFIG5L — — — — — —CP1CP0
300009h CONFIG5H CPD CPB — — — — — —
30000Ah CONFIG6L — — — — — —WRT1WRT0
30000Bh CONFIG6H WRTD WRTB WRTC
— — — — —
30000Ch CONFIG7L — — — — — — EBTR1 EBTR0
30000Dh CONFIG7H — EBTRB — — — — — —
Legend: Shaded cells are unimplemented.
Note: Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP operation or an
external programmer.
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
TBLWT*
TBLPTR = 0008FFh
PC = 003FFEh
PC = 00BFFEh
Register Values Program Memory
(1)
Configuration Bit Settings
TBLWT*
Boot Block
Block 0
Block 1
Results: All table writes disabled to Blockn whenever WRTn = 0.
Note 1: See Figure 24-5 for block boundaries.