Datasheet

PIC18F2221/2321/4221/4321 FAMILY
DS39689F-page 242 © 2009 Microchip Technology Inc.
20.8 Use of the CCP2 Trigger
An A/D conversion can be started by the Special Event
Trigger of the CCP2 module. This requires that the
CCP2M<3:0> bits (CCP2CON<3:0>) be programmed
as ‘1011’ and that the A/D module is enabled (ADON
bit is set). When the trigger occurs, the GO/DONE
bit
will be set, starting the A/D acquisition and conversion
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH:ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate T
ACQ time selected before
the Special Event Trigger sets the GO/DONE
bit (starts
a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
TABLE 20-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55
PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58
PIE1
PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58
IPR1 PSPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58
PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 58
PIE2
OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 58
IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 58
ADRESH A/D Result Register High Byte 57
ADRESL A/D Result Register Low Byte 57
ADCON0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 57
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 57
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 57
PORTA RA7
(2)
RA6
(2)
RA5 RA4 RA3 RA2 RA1 RA0 58
TRISA TRISA7
(2)
TRISA6
(2)
PORTA Data Direction Control Register 58
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 58
TRISB PORTB Data Direction Control Register 58
LATB PORTB Data Latch Register (Read and Write to Data Latch) 58
PORTE
— — — —RE3
(3)
RE2
(1)
RE1
(1)
RE0
(1)
58
TRISE
(1)
IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 58
LATE
(1)
— — — — — PORTE Data Latch Register 58
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These registers and/or bits are unimplemented on 28-pin devices and are read as ‘0’.
2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.