Datasheet

© 2009 Microchip Technology Inc. DS39689F-page 167
PIC18F2221/2321/4221/4321 FAMILY
18.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
18.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
2
C™)
- Full Master mode
- Slave mode (with address masking for both
10-bit and 7-bit addressing)
The I
2
C interface supports the following modes in
hardware:
•Master mode
• Multi-Master mode
• Slave mode
18.2 Control Registers
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2). The use
of these registers and their individual Configuration bits
differ significantly depending on whether the MSSP
module is operated in SPI or I
2
C mode.
Additional details are provided under the individual
sections.
18.3 SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four SPI
modes are supported. To accomplish communication,
typically three pins are used:
• Serial Data Out (SDO) – SDO
• Serial Data In (SDI) – SDI/SDA
• Serial Clock (SCK) – SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS
)
Figure 18-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 18-1: MSSP BLOCK DIAGRAM
(SPI MODE)
( )
Read Write
Internal
Data Bus
SSPSR reg
SSPM<3:0>
bit 0
Shift
Clock
SS
Control
Enable
Edge
Select
Clock Select
TMR2 Output
T
OSC
Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TX/RX in SSPSR
TRIS bit
2
SMP:CKE
SDO
SSPBUF reg
SDI/SDA
S
S
SCK/SCL