Information

© 2009 Microchip Technology Inc. DS80396B-page 3
PIC18F2220/2320/4220/4320
4. Module: Oscillator
The 32 kHz internal oscillator, INTRC, will be held
in Reset if either of the following is enabled:
• Power-up Timer
• High-Speed Crystal/Resonator with PLL
Enabled (HSPLL) Oscillator mode
Without the INTRC oscillator running, the Power-up
Timer and Phase Locked Loop (PLL) timer will not
expire and the PIC18F2220/2320/4220/4320
device will not exit Reset. This issue does not affect
the Watchdog Timer or any other mode.
The provided work arounds require only two
modifications to the Configuration Word values.
No additional changes to the application hardware
or software are necessary, except as noted below.
Work around: Power-up Timer
Disable the Power-up Timer by programming
PWRTEN
(CONFIG2L<0>) to ‘1’. This results in a
shorter time before the microcontroller begins to
execute code after power up or exiting from Sleep
mode or from Brown-out Reset (if enabled).
If a power-up delay is needed to ensure a stable
V
DD, consider using the Brown-out Reset (BOR)
feature. The BOR keeps the device in Reset until
the specified V
DD has been achieved.
This work around is available by programming the
BOR bit to ‘1’ and selecting BOR voltage bits with
BORV<1:0> bits in the CONFIG2L Configuration
Word.
If BOR
is not enabled and additional start-up delay
is needed, consider implementing an external
system supervisor to keep the microcontroller in
Reset until the V
DD has stabilized. Alternately,
consider use of an equivalent PIC18F4321 device.
Work around: HSPLL Oscillator Mode
Two work arounds are available through the
Configuration bits. Enabling either of the following
features permits the HSPLL mode to work
successfully:
• Two-Speed Start-up
• Fail-Safe Clock Monitor
Both options permit the microcontroller to start
from the 32 kHz INTRC after power-up, BOR, or
wake-up from Sleep mode. The options also
permit code to execute while PLL is waiting to lock.
The PLL lock time typically is 2 ms which results in
approximately 16 instruction executions before the
switch to the HSPLL clock occurs. If typical initial-
ization code is performed after a Power-on Reset
or Brown-out Reset, the impact of this work around
should be negligible.
If Sleep mode is used, both work arounds result in
code execution during PLL lock time. A software
delay may be needed to avoid executing time-crit-
ical code after wake-up. The OSTS
(OSCCON<3>) bit will set to indicate when the
HSPLL is ready and time-critical code can be
executed.
The Two-Speed Start-up and Fail-Safe Clock
Monitor work arounds switch the system clock
source from INTRC to HSPLL mode after a PLL
lock occurs. This is handled automatically by the
microcontroller and requires no additional soft-
ware or special monitoring. For more information,
see Section 2.7 “Clock Sources and Oscillator
Switching” in the “PIC18F2220/2320/4220/4320
Data Sheet” (DS39599).
Date Codes that pertain to this issue:
Engineering and production devices with a date
code of 0813 or later may be affected.