Information

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SPDIP 28 8-Bit 40 MHz I/O number 25

PIC18F2220/2320/4220/4320

The PIC18F2220/2320/4220/4320 Rev. C1 parts you

have received conform functionally to the Device Data

Sheet (DS39599G), except for the anomalies

described below. Any Data Sheet Clarification issues

related to the PIC18F2220/2320/4220/4320 will be

reported in a separate Data Sheet errata. Please check

the Microchip web site for any existing issues.

The following silicon errata apply only to

PIC18F2220/2320/4220/4320 devices with these

Device/Revision IDs:

All of the issues listed here will be addressed in future

revisions of the PIC18F2220/2320/4220/4320 silicon.

1. Module: Core (DAW Instruction)

The DAW instruction may improperly clear the

Carry bit (STATUS<0>) when executed.

Work around

Test the Carry bit state before executing the DAW

instruction. If the Carry bit is set, increment the

next higher byte to be added, using an instruction

such as INCFSZ (this instruction does not affect

any Status flags and will not overflow a BCD

nibble). After the DAW instruction has been

executed, process the Carry bit normally (see

Example 1).

EXAMPLE 1: PROCESSING THE CARRY

BIT DURING BCD ADDITIONS

Date Codes that pertain to this issue:

All engineering and production devices.

Part Number Device ID Revision ID

PIC18F2220 0000 0101 100 0 0110

PIC18F2320 0000 0101 000 0 0110

PIC18F4220 0000 0101 101 0 0110

PIC18F4320 0000 0101 001 0 0110

The Device IDs (DEVID1 and DEVID2) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in binary in the

format “DEVID2 DEVID1”.

MOVLW 0x80 ; .80 (BCD)

ADDLW 0x80 ; .80 (BCD)

BTFSC STATUS, C ; test C

INCFSZ byte2 ; inc next higher LSB

DAW

BTFSC STATUS, C ; test C

INCFSZ byte2 ; inc next higher LSB

This is repeated for each DAW instruction.

PIC18F2220/2320/4220/4320 Rev. C1 Silicon Errata

Summary of content (6 pages)

PAGE 1
PIC18F2220/2320/4220/4320 PIC18F2220/2320/4220/4320 Rev. C1 Silicon Errata The PIC18F2220/2320/4220/4320 Rev. C1 parts you have received conform functionally to the Device Data Sheet (DS39599G), except for the anomalies described below. Any Data Sheet Clarification issues related to the PIC18F2220/2320/4220/4320 will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues.
PAGE 2
PIC18F2220/2320/4220/4320 2. Module: MSSP (All I2C™ and SPI Modes) The Buffer Full flag bit (BF) of the SSPSTAT register (SSPSTAT<0>) may be inadvertently cleared, even when the SSPBUF register has not been read. This will occur only when the following two conditions occur simultaneously: • The four Least Significant bits of the BSR register are equal to 0Fh (BSR<3:0> = 1111) and • Any instruction that contains C9h in its 8 Least Significant bits (i.e.
PAGE 3
PIC18F2220/2320/4220/4320 4. Module: Oscillator The 32 kHz internal oscillator, INTRC, will be held in Reset if either of the following is enabled: • Power-up Timer • High-Speed Crystal/Resonator with PLL Enabled (HSPLL) Oscillator mode Without the INTRC oscillator running, the Power-up Timer and Phase Locked Loop (PLL) timer will not expire and the PIC18F2220/2320/4220/4320 device will not exit Reset. This issue does not affect the Watchdog Timer or any other mode.
PAGE 4
PIC18F2220/2320/4220/4320 REVISION HISTORY Rev A Document (9/2008) First revision of this document. Includes silicon issues 1 (Core – DAW Instruction), 2 (MSSP – All I2C™ and SPI modes), 3 (MSSP – SPI, Slave Mode) and 4 (INTRC Oscillator). Rev B Document (1/2009) Changed title of silicon issue 4 (Oscillator). DS80396B-page 4 © 2009 Microchip Technology Inc.
PAGE 5
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 6
WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.