Information

PIC18F2220/2320/4220/4320
DS80187D-page 2 © 2007 Microchip Technology Inc.
3. Module: Internal Oscillator Block
At high temperature (above 85°C) or low VDD
(below 2.5V), the IOFS bit (OSCCON<2>) may not
become set when the internal oscillator block is
selected as the system clock source for any
frequency above 31 kHz (OSCCON<6:4>
≠ 000).
The INTOSC output will stabilize at 8 MHz;
however, the IOFS bit may not become set.
Work around
If time critical code is to be executed, it should be
delayed by 1 ms following the operation that
enables the 8 MHz INTOSC output from the
internal oscillator block.
Date Codes that pertain to this issue:
All engineering and production devices.
4. Module: INTOSC
Incrementing or decrementing the value in the
OSCTUNE register may not have the expected
effect of shifting the INTRC or INTOSC output
frequencies. The OSCTUNE values beyond which
this happens may vary with temperatures above
70°C.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
5. Module: MSSP (All I
2
C™ and SPI Modes)
The Buffer Full flag bit (BF) of the SSPSTAT regis-
ter (SSPSTAT<0>) may be inadvertently cleared,
even when the SSPBUF register has not been
read. This will occur only when the following two
conditions occur simultaneously:
• The four Least Significant bits of the BSR
register are equal to 0Fh (BSR<3:0> = 1111)
and
• Any instruction that contains C9h in its 8 Least
Significant bits (i.e., register file addresses,
literal data, address offsets, etc.) is executed.
Work around
Identified work arounds will involve setting the
contents of BSR<3:0> to some value other than
0Fh.
In addition to those proposed below, other solutions
may exist.
1. When developing or modifying code, keep
these guidelines in mind:
• Assign 12-bit addresses to all variables.
This allows the assembler to know when
Access Banking can be used.
• Do not set the BSR to point to Bank 15
(BSR = 0Fh).
• Allow the assembler to manipulate the
Access bit present in most instructions.
Accessing the SFRs in Bank 15 will be done
through the Access Bank. Continue to use
the BSR to select all GPR Banks.
2. If accessing a part of Bank 15 is required and
the use of Access Banking is not possible,
consider using indirect addressing.
3. If pointing the BSR to Bank 15 is unavoidable,
review the absolute file listing. Verify that no
instructions contain C9h in the 8 Least Signifi-
cant bits while the BSR points to Bank 15
(BSR = 0Fh).
Date Codes that pertain to this issue:
All engineering and production devices.