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PIC18F2220/2320/4220/4320

The PIC18F2220/2320/4220/4320 Rev. B3 parts you

have received conform functionally to the Device Data

Sheet (DS39599F), except for the anomalies described

below.

All the problems listed here will be addressed in future

revisions of the PIC18F2220/2320/4220/4320 silicon.

The following silicon errata apply only to

PIC18F2220/2320/4220/4320 devices with these

Device/Revision IDs:

1. Module: Internal Oscillator Block

If the INTRC clock source was not started at POR

(any V

DD) and VDD is greater than 4.5V, the INTRC

clock source may not start or may require a long

delay when starting. The INTRC may not restart

when V

DD is lowered below 4.5V.

Features that depend on the operation of the

INTRC clock source may be affected. These

include the INTOSC output when exiting from

Sleep mode, the Watchdog Timer (WDT) if

enabled by firmware using the WDTCON register,

Two-Speed Start-ups during Reset or wake-up

from Sleep and the Fail-Safe Clock Monitor

(FSCM) when exiting Sleep mode.

The INTOSC frequency may rise very high (for

example, 9.5 MHz). The WDT and the FSCM may

simply not function. Two-Speed Start-ups may not

occur, but execution will start once the primary

clock source becomes ready.

Work around

Several work arounds may be used.

1. Enable the WDT in Configuration register,

CONFIG2H and place a CLRWDT instruction

somewhere in the main loop.

2. Configure the internal oscillator block as the

primary clock source using Configuration

3. Any technique that starts the INTRC at Reset

and does not disable it may be used.

4. Ensure that V

DD is below 4.5V when starting

the INTRC clock source.

There may be other work arounds.

Date Codes that pertain to this issue:

All engineering and production devices.

2. Module: Core (DAW Instruction)

The DAW instruction may improperly clear the

Carry bit (STATUS<0>) when executed.

Work around

Test the Carry bit state before executing the DAW

instruction. If the Carry bit is set, increment the

next higher byte to be added, using an instruction

such as INCFSZ (this instruction does not affect

any Status flags and will not overflow a BCD

nibble). After the DAW instruction has been

executed, process the Carry bit normally (see

Example 1).

EXAMPLE 1: PROCESSING THE CARRY

BIT DURING BCD ADDITIONS

Date Codes that pertain to this issue:

All engineering and production devices.

Part Number Device ID Revision ID

PIC18F2220 0000 0101 100 0 0100

PIC18F2320 0000 0101 000 0 0100

PIC18F4220 0000 0101 101 0 0100

PIC18F4320 0000 0101 001 0 0100

The Device IDs (DEVID1 and DEVID2) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in binary in the

format “DEVID2 DEVID1”.

MOVLW 0x80 ; .80 (BCD)

ADDLW 0x80 ; .80 (BCD)

BTFSC STATUS, C ; test C

INCFSZ byte2 ; inc next higher LSB

DAW

BTFSC STATUS, C ; test C

INCFSZ byte2 ; inc next higher LSB

This is repeated for each DAW instruction.

PIC18F2220/2320/4220/4320 Rev. B3 Silicon Errata

Summary of content (6 pages)

PAGE 1
PIC18F2220/2320/4220/4320 PIC18F2220/2320/4220/4320 Rev. B3 Silicon Errata The PIC18F2220/2320/4220/4320 Rev. B3 parts you have received conform functionally to the Device Data Sheet (DS39599F), except for the anomalies described below. All the problems listed here will be addressed in future revisions of the PIC18F2220/2320/4220/4320 silicon.
PAGE 2
PIC18F2220/2320/4220/4320 3. Module: Internal Oscillator Block At high temperature (above 85°C) or low VDD (below 2.5V), the IOFS bit (OSCCON<2>) may not become set when the internal oscillator block is selected as the system clock source for any frequency above 31 kHz (OSCCON<6:4> ≠ 000). The INTOSC output will stabilize at 8 MHz; however, the IOFS bit may not become set.
PAGE 3
PIC18F2220/2320/4220/4320 6. Module: MSSP (SPI, Slave Mode) In its current implementation, the SS (Slave Select) control signal generated by an external master processor may not be successfully recognized by the PIC® microcontroller operating in Slave Select mode (SSPM3:SSPM0 = 0100). In particular, it has been observed that faster transitions (those with shorter fall times) are more likely to be missed than slower transitions.
PAGE 4
PIC18F2220/2320/4220/4320 REVISION HISTORY Rev A Document (04/2004) First revision of this document, silicon issues 1 (Internal Oscillator Block), 2 (Core – DAW Instruction), 3 (Internal Oscillator Block), 4 (INTOSC), 5 (MSSP – All I2C and SPI Modes), 6 (MSSP – SPI, Slave Mode), 7 (Data EEPROM) and data sheet clarification issues 1 (RE3 Pin), 2 (Timer1 Oscillator), 3 (Enhanced PWM Module Block Diagram), 4 (Enabling SPI I/O), 5 (DC Characteristics), 6 (DC Characteristics) and 7 (LVD Characteristics).
PAGE 5
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 6
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