Information

© 2007 Microchip Technology Inc. DS80156G-page 3
PIC18F2220/2320/4220/4320
6. Module: MSSP (SPI, Slave Mode)
In its current implementation, the SS (Slave
Select) control signal generated by an external
master processor may not be successfully recog-
nized by the PIC
®
microcontroller operating in
Slave Select mode (SSPM3:SSPM0 = 0100). In
particular, it has been observed that faster transi-
tions (those with shorter fall times) are more likely
to be missed than slower transitions.
Work around
Insert a series resistor between the source of the
SS
signal and the corresponding SS input line of
the microcontroller. The value of the resistor is
dependent on both the application system’s
characteristics and process variations between
microcontrollers. Experimentation and thorough
testing is encouraged.
This is a recommended solution; others may exist.
Date Codes that pertain to this issue:
All engineering and production devices.
7. Module: Data EEPROM
When writing to the data EEPROM, the contents of
the data EEPROM memory may not be written as
expected.
Work around
Either of two work arounds can be used:
1. Before beginning any writes to the data
EEPROM, enable the LVD (any voltage) and
wait for the internal voltage reference to
become stable. LVD interrupt requests may be
ignored. Once the LVD voltage reference is
stable, perform all EEPROM writes normally.
When writes have been completed, the LVD
may be disabled.
2. Configure the BOR as enabled (any voltage).
Select a threshold below V
DD to allow normal
operation. If V
DD is below the BOR threshold,
the device will be held in BOR Reset.
Date Codes that pertain to this issue:
All engineering and production devices.
8. Module: Oscillator Configurations
(OSCTUNE Register)
The INTRC and INTOSC clock sources are both
adjusted using the OSCTUNE register and may
not be adjusted separately. Peripherals that use
the INTRC clock source (WDT and FSCM) also
are affected.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
9. Module: Oscillator Configurations
(OSCTUNE 2 Register)
This revision of silicon does not have the
OSCTUNE 2 register. Address F9Bh is not
implemented.
Work around
If the INTRC frequency is to be adjusted, modify
the contents of the OSCTUNE register.
Date Codes that pertain to this issue:
All engineering and production devices.
10. Module: Oscillator Configurations
(INTOSC Clock Source)
The INTOSC clock source requires more start-up
time than what is stated in the data sheet. The
IOFS bit (OSCCON<2>) will indicate the INTOSC
has settled in approximately 4 ms.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.