Datasheet

PIC18F2220/2320/4220/4320
DS39599G-page 64 © 2007 Microchip Technology Inc.
EEADR EEPROM Address Register 0000 0000 48, 81
EEDATA EEPROM Data Register 0000 0000 48, 84
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 48, 72, 81
EECON1 EEPGD CFGS
— FREE WRERR WREN WR RD xx-0 x000 48, 73, 82
IPR2 OSCFIP CMIP
— EEIP BCLIP LVDIP TMR3IP CCP2IP 11-1 1111 49, 97
PIR2 OSCFIF CMIF
— EEIF BCLIF LVDIF TMR3IF CCP2IF 00-0 0000 49, 93
PIE2 OSCFIE CMIE
— EEIE BCLIE LVDIE TMR3IE CCP2IE 00-0 0000 49, 95
IPR1 PSPIP
(5)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 49, 96
PIR1 PSPIF
(5)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 49, 92
PIE1 PSPIE
(5)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 49, 94
OSCTUNE
— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 23, 49
TRISE
(5)
IBF OBF IBOV PSPMODE — Data Direction bits for PORTE 0000 -111 49, 112
TRISD
(5)
Data Direction Control Register for PORTD 1111 1111 49, 110
TRISC Data Direction Control Register for PORTC 1111 1111 49, 108
TRISB Data Direction Control Register for PORTB 1111 1111 49, 106
TRISA TRISA7
(2)
TRISA6
(1)
Data Direction Control Register for PORTA 1111 1111 49, 103
LATE
(5)
— — — — — Read/Write PORTE Data Latch ---- -xxx 49, 113
LATD
(5)
Read/Write PORTD Data Latch xxxx xxxx 49, 110
LATC Read/Write PORTC Data Latch xxxx xxxx 49, 108
LATB Read/Write PORTB Data Latch xxxx xxxx 49, 106
LATA LATA<7>
(2)
LATA<6>
(1)
Read/Write PORTA Data Latch xxxx xxxx 49, 103
PORTE
(5)
— — — —RE3
(6)
Read PORTE pins,
Write PORTE Data Latch
---- qxxx 49, 113
PORTD
(5)
Read PORTD pins, Write PORTD Data Latch xxxx xxxx 49, 110
PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 49, 108
PORTB Read PORTB pins, Write PORTB Data Latch
(4)
xxxx xxxx 49, 106
PORTA RA7
(2)
RA6
(1)
Read PORTA pins, Write PORTA Data Latch xx0x 0000 49, 103
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details on
page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read
as ‘0’ in all other oscillator modes.
2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read as ‘0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: If PBADEN = 0, PORTB<4:0> are configured as digital inputs and read unknown and if PBADEN = 1, PORTB<4:0> are configured as
analog inputs and read as ‘0’ following a Reset.
5: These registers and/or bits are not implemented on the PIC18F2X20 devices and read as 0x00.
6: The RE3 port bit is available as an input only pin only in 40-pin devices when Master Clear functionality is disabled (CONFIG3H<7> = 0).