Datasheet

© 2007 Microchip Technology Inc. DS39599G-page 63
PIC18F2220/2320/4220/4320
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0000 q000 27, 47
LVDCON
— — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 47, 233
WDTCON
— — — — — — —SWDTEN--- ---0 47, 247
RCON IPEN
— —RITO PD POR BOR 0--1 11q0 45, 69, 98
TMR1H Timer1 Register High Byte xxxx xxxx 47, 125
TMR1L Timer1 Register Low Byte xxxx xxxx 47, 125
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 47, 121
TMR2 Timer2 Register 0000 0000 47, 127
PR2 Timer2 Period Register 1111 1111 47, 127
T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 47, 127
SSPBUF MSSP Receive Buffer/Transmit Register xxxx xxxx 47, 156,
164
SSPADD MSSP Address Register in I
2
C™ Slave mode. MSSP Baud Rate Reload Register in I
2
C Master mode. 0000 0000 47, 164
SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 47, 156,
165
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 47, 157,
166
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 47, 167
ADRESH A/D Result Register High Byte xxxx xxxx 48, 220
ADRESL A/D Result Register Low Byte xxxx xxxx 48, 220
ADCON0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 48, 211
ADCON1
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 48, 212
ADCON2 ADFM
— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 48, 213
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 48, 134
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 48, 134
CCP1CON P1M1
(5)
P1M0
(5)
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 48, 133,
141
CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 48, 134
CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 48, 134
CCP2CON
— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 48, 133
PWM1CON
(5)
PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 48, 149
ECCPAS
(5)
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 48, 150
CVRCON CVREN CVROE CVRR
— CVR3 CVR2 CVR1 CVR0 000- 0000 48, 227
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 48, 221
TMR3H Timer3 Register High Byte xxxx xxxx 48, 131
TMR3L Timer3 Register Low Byte xxxx xxxx 48, 131
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
TMR3CS TMR3ON 0000 0000 48, 129
SPBRG USART Baud Rate Generator 0000 0000 48, 198
RCREG USART Receive Register 0000 0000 48, 204,
203
TXREG USART Transmit Register 0000 0000 48, 202,
203
TXSTA CSRC TX9 TXEN SYNC
— BRGH TRMT TX9D 0000 -010 48, 196
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 48, 197
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details on
page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read
as ‘0’ in all other oscillator modes.
2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read as ‘0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: If PBADEN = 0, PORTB<4:0> are configured as digital inputs and read unknown and if PBADEN = 1, PORTB<4:0> are configured as
analog inputs and read as ‘0’ following a Reset.
5: These registers and/or bits are not implemented on the PIC18F2X20 devices and read as 0x00.
6: The RE3 port bit is available as an input only pin only in 40-pin devices when Master Clear functionality is disabled (CONFIG3H<7> = 0).