Datasheet

PIC18F2220/2320/4220/4320
DS39599G-page 62 © 2007 Microchip Technology Inc.
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details on
page:
TOSU
— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 46, 54
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 46, 54
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 46, 54
STKPTR STKFUL STKUNF
— Return Stack Pointer 00-0 0000 46, 55
PCLATU
— —bit 21
(3)
Holding Register for PC<20:16> ---0 0000 46, 56
PCLATH Holding Register for PC<15:8> 0000 0000 46, 56
PCL PC Low Byte (PC<7:0>) 0000 0000 46, 56
TBLPTRU
— — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 46, 74
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 46, 74
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 46, 74
TABLAT Program Memory Table Latch 0000 0000 46, 74
PRODH Product Register High Byte xxxx xxxx 46, 85
PRODL Product Register Low Byte xxxx xxxx 46, 85
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 46, 89
INTCON2 RBPU
INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP1111 -1-1 46, 90
INTCON3 INT2IP INT1IP
—INT2IEINT1IE— INT2IF INT1IF 11-0 0-00 46, 91
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) n/a 46, 66
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) n/a 46, 66
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) n/a 46, 66
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) n/a 46, 66
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register) n/a 46, 66
FSR0H
— — — — Indirect Data Memory Address Pointer 0 High ---- 0000 46, 66
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 46, 66
WREG Working Register xxxx xxxx 46
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) n/a 46, 66
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) n/a 46, 66
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) n/a 46, 66
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) n/a 46, 66
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register) n/a 46, 66
FSR1H
— — — — Indirect Data Memory Address Pointer 1 High ---- 0000 47, 66
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 47, 66
BSR
— — — — Bank Select Register ---- 0000 47, 65
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) n/a 47, 66
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) n/a 47, 66
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) n/a 47, 66
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) n/a 47, 66
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register) n/a 47, 66
FSR2H
— — — — Indirect Data Memory Address Pointer 2 High ---- 0000 47, 66
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 47, 66
STATUS
— — —NOVZDCC---x xxxx 47, 68
TMR0H Timer0 Register High Byte 0000 0000 47, 119
TMR0L Timer0 Register Low Byte xxxx xxxx 47, 119
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 47, 117
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read
as ‘0’ in all other oscillator modes.
2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read as ‘0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: If PBADEN = 0, PORTB<4:0> are configured as digital inputs and read unknown and if PBADEN = 1, PORTB<4:0> are configured as
analog inputs and read as ‘0’ following a Reset.
5: These registers and/or bits are not implemented on the PIC18F2X20 devices and read as 0x00.
6: The RE3 port bit is available as an input only pin only in 40-pin devices when Master Clear functionality is disabled (CONFIG3H<7> = 0).