Datasheet

© 2007 Microchip Technology Inc. DS39599G-page 51
PIC18F2220/2320/4220/4320
FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR
TIED TO VDD)
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
0V
1V
5V
T
PWRT
TOST
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
PLL Time-out
TPLL
Note: TOST = 1024 clock cycles.
T
PLL ≈ 2 ms max. First three stages of the PWRT timer.