Datasheet

PIC18F2220/2320/4220/4320
DS39599G-page 46 © 2007 Microchip Technology Inc.
TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU 2220 2320 4220 4320 ---0 0000 ---0 0000 ---0 uuuu
(3)
TOSH 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
(3)
TOSL 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
(3)
STKPTR 2220 2320 4220 4320 uu-0 0000 00-0 0000 uu-u uuuu
(3)
PCLATU 2220 2320 4220 4320 ---0 0000 ---0 0000 ---u uuuu
PCLATH 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
PCL 2220 2320 4220 4320 0000 0000 0000 0000 PC + 2
(2)
TBLPTRU 2220 2320 4220 4320 --00 0000 --00 0000 --uu uuuu
TBLPTRH 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
TABLAT 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu
PRODH 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 2220 2320 4220 4320 0000 000x 0000 000u uuuu uuuu
(1)
INTCON2 2220 2320 4220 4320 1111 -1-1 1111 -1-1 uuuu -u-u
(1)
INTCON3 2220 2320 4220 4320 11-0 0-00 11-0 0-00 uu-u u-uu
(1)
INDF0 2220 2320 4220 4320 N/A N/A N/A
POSTINC0 2220 2320 4220 4320 N/A N/A N/A
POSTDEC0 2220 2320 4220 4320 N/A N/A N/A
PREINC0 2220 2320 4220 4320 N/A N/A N/A
PLUSW0 2220 2320 4220 4320 N/A N/A N/A
FSR0H 2220 2320 4220 4320 ---- xxxx ---- uuuu ---- uuuu
FSR0L 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 2220 2320 4220 4320 N/A N/A N/A
POSTINC1 2220 2320 4220 4320 N/A N/A N/A
POSTDEC1 2220 2320 4220 4320 N/A N/A N/A
PREINC1 2220 2320 4220 4320 N/A N/A N/A
PLUSW1 2220 2320 4220 4320 N/A N/A N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.