Datasheet

© 2007 Microchip Technology Inc. DS39599G-page 39
PIC18F2220/2320/4220/4320
TABLE 3-3: ACTIVITY AND EXIT DELAY ON WAKE-UP FROM SLEEP MODE OR
ANY IDLE MODE (BY CLOCK SOURCES)
Clock in
Power-Managed
Mode
Primary System
Clock
Power-Managed
Mode Exit Delay
Clock Ready
Status Bit
(OSCCON)
Activity During Wake-up from
Power-Managed Mode
Exit by Interrupt Exit by Reset
Primary System
Clock
(PRI_IDLE mode)
LP, XT, HS
5-10 μs
(5)
OSTS
CPU and peripherals
clocked by primary clock
and executing
instructions.
Not clocked or
Two-Speed
Start-up
(if enabled)
(3)
.
HSPLL
EC, RC, INTRC
(1)
—
INTOSC
(2)
IOFS
T1OSC or INTRC
(1)
LP, XT, HS OST
OSTS
CPU and peripherals
clocked by selected
power-managed mode
clock and executing
instructions until primary
clock source becomes
ready.
HSPLL OST + 2 ms
EC, RC, INTRC
(1)
5-10 μs
(5)
—
INTOSC
(2)
5-10 μs
(4)
IOFS
INTOSC
(2)
LP, XT, HS OST
OSTS
HSPLL OST + 2 ms
EC, RC, INTRC
(1)
5-10 μs
(5)
—
INTOSC
(2)
None IOFS
Sleep mode
LP, XT, HS OST
OSTS
Not clocked or
Two-Speed Start-up (if
enabled) until primary
clock source becomes
ready
(3)
.
HSPLL OST + 2 ms
EC, RC, INTRC
(1)
5-10 μs
(5)
—
INTOSC
(2)
5-10 μs
(4)
IOFS
Note 1: In this instance, refers specifically to the INTRC clock source.
2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
3: Two-Speed Start-up is covered in greater detail in Section 23.3 “Two-Speed Start-up”.
4: Execution continues during the INTOSC stabilization period.
5: Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other
required delays (see Section 3.3 “Idle Modes”).