Datasheet

© 2007 Microchip Technology Inc. DS39599G-page 387
PIC18F2220/2320/4220/4320
Timing Diagrams and Specifications ................................ 328
A/D Conversion Requirements ................................ 346
Capture/Compare/PWM Requirements ................... 334
CLKO and I/O Requirements ................................... 330
DC Characteristics - Internal RC Accuracy .............. 329
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 336
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 337
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 338
Example SPI Slave Mode
Requirements (CKE = 1) .................................. 339
External Clock Requirements .................................. 328
I
2
C Bus Data Requirements (Slave Mode) .............. 341
Master SSP I
2
C Bus Data Requirements ................ 343
Master SSP I
2
C Bus Start/Stop Bits
Requirements ................................................... 342
Parallel Slave Port Requirements
(PIC18F4X20) .................................................. 335
PLL Clock ................................................................. 329
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 332
Timer0 and Timer1 External Clock
Requirements ................................................... 333
USART Synchronous Receive Requirements ......... 344
USART Synchronous Transmission
Requirements ................................................... 344
Top-of-Stack Access .......................................................... 54
TRISE Register
PSPMODE Bit .......................................................... 109
TSTFSZ ............................................................................ 298
Two-Speed Start-up ................................................. 237, 248
Two-Word Instructions
Example Cases .......................................................... 58
TXSTA Register
BRGH Bit ................................................................. 198
U
USART ............................................................................. 195
Asynchronous Mode ................................................ 202
Associated Registers, Receive ........................ 205
Associated Registers, Transmit ....................... 203
Receiver ........................................................... 204
Transmitter ....................................................... 202
Baud Rate Generator (BRG) .................................... 198
Associated Registers ....................................... 198
Baud Rate Formula .......................................... 198
Baud Rates, Asynchronous Mode
(BRGH = 0, Low Speed) .......................... 199
Baud Rates, Asynchronous Mode
(BRGH = 1, High Speed) ......................... 200
Baud Rates, Synchronous Mode
(SYNC = 1) .............................................. 201
High Baud Rate Select (BRGH Bit) .................. 198
Operation in Power-Managed Mode ................ 198
Sampling .......................................................... 198
Serial Port Enable (SPEN Bit) ................................. 195
Setting Up 9-Bit Mode with Address Detect ............. 204
Synchronous Master Mode ...................................... 206
Associated Registers, Reception ..................... 208
Associated Registers, Transmit ....................... 207
Reception ........................................................ 208
Transmission ................................................... 206
Synchronous Slave Mode ........................................ 209
Associated Registers, Receive ........................ 210
Associated Registers, Transmit ....................... 209
Reception ........................................................ 210
Transmission ................................................... 209
V
Voltage Reference Specifications .................................... 322
W
Watchdog Timer (WDT) ............................................237, 246
Associated Registers ............................................... 247
Control Register ....................................................... 246
During Oscillator Failure .......................................... 249
Programming Considerations .................................. 246
WCOL .............................................................................. 183
WCOL Status Flag ............................................ 183, 185, 188
WWW Address ................................................................ 389
WWW, On-Line Support ...................................................... 5
X
XORLW ............................................................................ 298
XORWF ........................................................................... 299